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  1. 17 Jul, 2019 1 commit
    • Jun Nie's avatar
      plat: imx7: refactor code for reuse · c5937f2d
      Jun Nie authored 
      

For the iMX7 SOCs, part of the code for platform
setup implementation can be reused and made
common for all these SoCs. This patch extracts
the common part for reuse.
Signed-off-by: default avatarJun Nie <jun.nie@linaro.org>
Change-Id: I42fd4167e6903416df96a0159a046abf3896e878
      c5937f2d
  3. 04 Jul, 2019 1 commit
  5. 01 Jul, 2019 1 commit
  7. 28 Jun, 2019 2 commits
  9. 21 May, 2019 1 commit
  11. 20 May, 2019 2 commits
  13. 13 May, 2019 1 commit
  15. 09 May, 2019 1 commit
  17. 08 May, 2019 2 commits
  19. 12 Apr, 2019 1 commit
    • Ambroise Vincent's avatar
      Mbed TLS: Remove weak heap implementation · 2374ab17
      Ambroise Vincent authored 
      

The implementation of the heap function plat_get_mbedtls_heap() becomes
mandatory for platforms supporting TRUSTED_BOARD_BOOT.

The shared Mbed TLS heap default weak function implementation is
converted to a helper function get_mbedtls_heap_helper() which can be
used by the platforms for their own function implementation.

Change-Id: Ic8f2994e25e3d9fcd371a21ac459fdcafe07433e
Signed-off-by: default avatarAmbroise Vincent <ambroise.vincent@arm.com>
      2374ab17
  21. 08 Apr, 2019 1 commit
  23. 03 Apr, 2019 2 commits
  25. 13 Mar, 2019 1 commit
    • Jacky Bai's avatar
      plat: imx8m: Add the basic support for imx8mm · 179f82a2
      Jacky Bai authored 
      

The i.MX8M Mini is new SOC of the i.MX8M family. it is
focused on delivering the latest and greatest video and
audio experience combining state-of-the-art media-specific
features with high-performance processing while optimized
for lowest power consumption. The i.MX 8M Mini Media Applications
Processor is  14nm FinFET product of the growing i.MX8M family
targeting the consumer & industrial market. It is built in 14LPP
to achieve both high performance and low power consumption
and relies on a powerful fully coherent core complex based on
a quad Cortex-A53 cluster with video and graphics accelerators

this patch add the basic support for i.MX8MM.
Signed-off-by: default avatarJacky Bai <ping.bai@nxp.com>
      179f82a2
  27. 12 Mar, 2019 1 commit
  29. 01 Mar, 2019 1 commit
    • Anson Huang's avatar
      imx: make sure GIC redistributor is awake before initialization · e655fefc
      Anson Huang authored 
      

GICR_WAKER.ProcessorSleep can only be set to zero when:
— GICR_WAKER.Sleep bit[0] == 0.
— GICR_WAKER.Quiescent bit[31] == 0.

On some platforms, when system reboot with GIC in sleep
mode but with power ON, such as on NXP's i.MX8QM, Linux
kernel enters suspend but could be requested to reboot,
and GIC is in sleep mode and it is inside a power domain
which is ON in this scenario, when CPU reset, the GIC
driver trys to set CORE's redistributor interface to awake,
with GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31]
both set, the ProcessorSleep bit[1] will never be clear
and cause system hang.

This patch makes sure GICR_WAKER.Sleep bit[0] and
GICR_WAKER.Quiescent bit[31] are both zeor before clearing
ProcessorSleep bit[1].
Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
      e655fefc
  31. 22 Feb, 2019 1 commit
  33. 12 Feb, 2019 1 commit
  35. 01 Feb, 2019 1 commit
  37. 29 Jan, 2019 2 commits
    • Anson Huang's avatar
      imx: power optimization for i.mx8qx · e6cf7a46
      Anson Huang authored 
      

Current implementation of i.MX8QX power management related
features does NOT optimize power number, all system resources
like CCI, DDR, and A cluster etc. are kept in STBY mode (powered
ON) when system suspend or CPU hotplug.

To lower the power number, OFF mode should be adopted for those
system resources whenever they can be OFF, A cluster will be OFF
if the CPUs in the cluster are all off line, DDR/MU/DB can be OFF
if system suspend, IRQ steer can be OFF if the wakeup source is
belonged to system controller partition, so wakeup source runtime
check is used to determine if IRQ steer can be OFF before system
suspend.

If resources are powered off for suspend, they should be restored
properly after system resume.
Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
      e6cf7a46
    • Anson Huang's avatar
      imx: power optimization for i.mx8qm · 3a2b5199
      Anson Huang authored 
      

Current implementation of i.MX8QM power management related
features does NOT optimize power number, all system resources
like CCI, DDR, and A cluster etc. are kept in STBY mode (powered
ON) when system suspend or CPU hotplug.

To lower the power number, OFF mode should be adopted for those
system resources whenever they can be OFF, A cluster will be OFF
if the CPUs in the cluster are all off line, DDR/MU/DB can be OFF
if system suspend, IRQ steer can be OFF if the wakeup source is
belonged to system controller partition, so wakeup source runtime
check is used to determine if IRQ steer can be OFF before system
suspend.

If resources are powered off for suspend, they should be restored
properly after system resume.
Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
      3a2b5199
  39. 24 Jan, 2019 2 commits
  41. 18 Jan, 2019 8 commits
  43. 17 Jan, 2019 3 commits
    • Anson Huang's avatar
      imx: add cpu-freq SIP runtime service support · d3996c59
      Anson Huang authored 
      

On i.MX8QM/i.MX8QX with system controller inside, the CPU's clock
rate is managed by SCFW(system controller firmware) and can ONLY be
changed from secure world, so SIP runtime service is needed for
setting CPU's clock rate, this patch adds cpu-freq SIP runtime service
support.
Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
      d3996c59
    • Anson Huang's avatar
      imx: add imx8qm/imx8qx SRTC SIP runtime service support · 025514ba
      Anson Huang authored 
      

On i.MX8QM/i.MX8QX with system controller inside, the SRTC is
managed by SCFW(system controller firmware) and some functions
like setting SRTC's time etc. can ONLY be requested from secure
world, so SIP runtime service is needed for such kind of operations,
this patch adds SRTC SIP runtime service support for i.MX8QM and
i.MX8QX.
Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
      025514ba
    • Anson Huang's avatar
      Support for NXP's i.MX8 SoCs timer IPC · 1552df5d
      Anson Huang authored 
      

NXP's i.MX8 SoCs have system controller (M4 core) which takes
control of timer management, including watchdog, srtc and system
counter etc., other clusters like Cortex-A35 can send out command
via MU (Message Unit) to system controller for timer operation.

This patch adds timer IPC(inter-processor communication) support.
Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
      1552df5d
  45. 15 Jan, 2019 2 commits
    • Anson Huang's avatar
      imx: make imx uart work for debug mode · 2e8ab4f5
      Anson Huang authored 
      

With DEBUG_CONSOLE enabled, build will fail for imx8mq platform:

./build/imx8mq/release/bl31/imx8mq_bl31_setup.o:
In function `bl31_early_platform_setup2':
imx8mq_bl31_setup.c:(.text.bl31_early_platform_setup2+0x40):
	undefined reference to `console_uart_register'
Makefile:741: recipe for target 'build/imx8mq/release/bl31/bl31.elf' failed
make: *** [build/imx8mq/release/bl31/bl31.elf] Error 1

Besides, the .console_flush callback needs to be added to avoid
panic when debug mode is enabled, since the console_flush() will
call it without checking whether the function callback is valid.
Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
      2e8ab4f5
    • Anson Huang's avatar
      imx: add necessary lpuart console_flush callback for debug · f1ac7964
      Anson Huang authored 
      

Current lpuart driver does NOT implement .console_flush callback,
if debug console is enabled, the console_flush() will call the
undefined .console_flush callback(NULL) for lpuart and leak to
panic, this patch adds .console_flush callback to make lpuart work
for debug mode.
Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
      f1ac7964
  47. 04 Jan, 2019 1 commit
    • Antonio Nino Diaz's avatar
      Sanitise includes across codebase · 09d40e0e
      Antonio Nino Diaz authored 
      Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca339

 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      09d40e0e