GitLab

plat: marvell: armada: a3k: When WTP is empty do not define variables and targets which depends on it

Some of targets (e.g. mrvl_flash) depends on WTP build option. Other
targets (e.g. fip) can be build also without WTP build option as they do
not depend on it.

This change put all A3720 variables and targets which depends on WTP into
conditional if-endif section, so they are not defined when user has not
supplied WTP build option.

Target mrvl_flash is defined also when WTP was not specified and in this
case it just print error message to help user.

Variables which do not depend on WTP are moved to the top of
a3700_common.mk file.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Idb3892233586a0afca3e0e6564279641d2e4b960

* changes:
  docs: marvell: update mv_ddr branch
  plat: marvell: armada: a3k: rename the UART images archive
  plat: marvell: armada: a3k: allow image load to RAM address 0
  marvell: comphy: cp110: add support for USB comphy polarity invert
  marvell: comphy: cp110: add support for SATA comphy polarity invert
  marvell: comphy: cp110: implement erratum IPCE_COMPHY-1353
  drivers: marvell: mochi: Update AP incoming masters secure level
  plat: marvell: armada: add ccu window for workaround errata-id 3033912
  plat: marvell: ap806: implement workaround for errata-id FE-4265711

Now that the BLE image sources (mv_ddr) are updated, reflect
the proper branch in the Armada build howto.

Change-Id: I959d1343d0dfdd681c7e39bdcaed9b36aaddfca1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

Add *.bin extension to UART recovery images archive name.
Such naming will cause the UART recovery images to be copied to the
Buildroot output folder upon flash image build.

Change-Id: I6992df1ab2ded725bed58e5baf245ae92c4cb289
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

Marvell uses RAM address 0x0 for loading BL33 stage images.
When ATF is built with DEBUG=1, its IO subsystem fails on
assert checking the destination RAM address != 0.
This patch adds PLAT_ALLOW_ZERO_ADDR_COPY to A3K platform
allowing to bypass the above check in debug mode.

Change-Id: I687e35cb2e9dc3166bdaa81b3904c20b784c5c6a
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

The polarity inversion for USB was not tested due to lack of hw design
which requires it. Currently all supported boards doesn't require USB
phy polarity inversion, therefore COMPHY_POLARITY_NO_INVERT is set for
all boards. Enable the option for the ones that need it.

Change-Id: Ia5f2ee313a93962e94963e2dd8a759ef6d9da369
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

The cp110 comphy has ability to invert RX and/or TX polarity. Polarity
depends on board design. Currently all supported boards doesn't require
SATA phy polarity invert, therefore COMPHY_POLARITY_NO_INVERT is set for
all boards.

Change-Id: Ifd0bc6aaf8a76a0928132b197422f3193cf020d5
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

According to erratum IPCE_COMPHY-1353 the TX_IDLE bit should
be toggled in addition to the XFI/SFI PHY reset.

Change-Id: Idd2c2abfcb2f960caa01e6d69db524c2e4734f50
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

Do not force non-secure access level for PIDI masters when LLC_SRAM
is enabled. The EIP197 is located on CP0 and need to access secure
SRAM in AP LLC. This requires EIP197 DMA to have AXPROT[1]=0 and not
changed when forwarded to address decoding tables.

Change-Id: I8962db94a124350c14220ba6d0364d294ae4664a
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

Added ccu window to allow access to addresses
in the range [0xf100_0000, 0xf1ff_ffff].

Change-Id: I63ee68338d674114d01cd627198dc907653493e8
Signed-off-by: Alex Leibovich <alexl@marvell.com>

ERRATA ID: FE-4265711 - Incorrect CNTVAL reading

CNTVAL reflects the global system counter value in binary format.
Due to this erratum, the CNTVAL value presented to the processor
may be incorrect for several clock cycles.

Workaround: Override the default value of AP Register Device General
control 20 [19:16] and AP Register Device General Control 21 [11:8]
to the value of 0x3.

Change-Id: I1705608d08acd9631ab98d6f7ceada34d6b8336f
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

Cortex A76 erratum 1868343 is a Cat B erratum, present in older
revisions of the Cortex A76 processor core.  The workaround is to
set a bit in the CPUACTLR_EL1 system register, which delays instruction
fetch after branch misprediction. This workaround will have a small
impact on performance.

This workaround is the same as workarounds for errata 1262606 and
1275112, so all 3 have been combined into one function call.

SDEN can be found here:
https://documentation-service.arm.com/static/5f2bed6d60a93e65927bc8e7

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7f2f9965f495540a1f84bb7dcc28aff45d6cee5d

Update the libfdt source files, the upstream commit is 73e0f143b73d
("libfdt: fdt_strerror(): Fix comparison warning").

This brings us the fixes for the signed/unsigned comparison warnings,
so platforms can enable -Wsign-compare now.

Change-Id: I303d891c82ffea0acefdde27289339db5ac5a289
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

With -Wsign-compare, compilers issue a warning in the SPMD code:
====================
services/std_svc/spmd/spmd_pm.c:35:22: error: comparison of integer
expressions of different signedness: 'int' and 'unsigned int'
[-Werror=sign-compare]
   35 |  if ((id < 0) || (id >= PLATFORM_CORE_COUNT)) {
      |                      ^~
cc1: all warnings being treated as errors
====================

Since we just established that "id" is positive, we can safely cast it
to an unsigned type to make the comparison have matching types.

Change-Id: I6ef24804c88136d7e3f15de008e4fea854f10ffe
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Morello platform has a SCP which brings the primary Rainier CPU
out of reset which starts executing at BL31.

This patch provides documentation support for Morello platform.
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: I38f596668e2b14862d543fabc04549ff34bfb8a2

stm32mp15_optee_defconfig has been dropped from U-Boot as it became
identical to stm32mp15_trusted_defconfig.

Furthermore give a hint how OP-TEE is supposed to be installed.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: Id8f0bd84a87e3a62072dd4405aadddcdd3511213

This patch makes changes required to get the morello
platform working with the tip of TF-A.

Change-Id: I095006615c9959bba49fcc75b52e1de7d7486309
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

This patch migrates the mbedcrypto dependency for TF-A
to mbedTLS repo v2.24.0 which is the latest release tag.
The relevant documentation is updated to reflect the
use of new version.

Change-Id: I116f44242e8c98e856416ea871d11abd3234dac1
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

* changes:
  stm32mp1: correct crash console GPIO alternate configuration
  stm32mp1: add plat_panic_handler function
  stm32mp1: update plat_report_exception
  Align AARCH32 version of debug.S with AARCH64

* changes:
  arm_fpga: Add platform documentation
  arm_fpga: Add post-build linker script
  arm_fpga: Add ROM trampoline
  arm_fpga: Add devicetree file
  arm_fpga: Remove SPE PMU DT node if SPE is not available
  arm_fpga: Adjust GICR size in DT to match number of cores
  fdt: Add function to adjust GICv3 redistributor size
  drivers: arm: gicv3: Allow detecting number of cores

As the Arm Ltd. FPGA port is now working for all existing images, add
some documentation file.

Change-Id: I9e2c532ed15bbc121bb54b3dfc1bdfee8f1443a6
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

For the Arm Ltd. FPGAs to run, we need to load several payloads into the
FPGA's memory:
- Some trampoline code at address 0x0, to jump to BL31's entry point.
- The actual BL31 binary at the beginning of DRAM.
- The (generic) DTB image to describe the hardware.
- The actual non-secure payloads (kernel, ramdisks, ...)

The latter is application specific, but the first three blobs are rather
generic.
Since the uploader tool supports ELF binaries, it seems helpful to
combine these three images into one .axf file, as this also simplifies
the command line.

Add a post-build linker script, that combines those three bits into one
ELF file, together with their specific load addresses.
Include a call to "ld" with this linker script in the platform Makefile,
so it will be build automatically. The result will be called "bl31.axf".

Change-Id: I4a90da16fa1e0e83b51d19e5b1daf61f5a0bbfca
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

The application cores of the FPGAs used in Arm Ltd. start execution at
address 0x0. This is the location of some (emulated) ROM area (which can
be written to by the uploading tool).
Since the arm_fpga port is configured to run from DRAM, we load BL31 to
the beginning of DRAM (mapped at 2GB). This requires some small
trampoline code in the "ROM" to jump to the BL31 entry point.

To avoid some extra magic binary, add a tiny assembly file with that
trivial jump instruction to the tree, so this binary can be created
alongside BL31.

Change-Id: I9e4439fc0f093fa24dd49a8377c9edb030fbb477
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

The FPGA images used in Arm Ltd. focus on CPU cores, so they share a
common platform, with a minimal set of peripherals (interconnect, GIC,
UART).
This allows to support most platforms with a single devicetree file.
The topology and number of CPU cores differ, but those will added at
runtime, in BL31. Other adjustments (GICR size, SPE node, command line)
are also done at this point.

Add the common devicetree file to TF-A's build system, so it can be
build together with BL31. At runtime, the resulting .dtb file should be
uploaded to the address given with FPGA_PRELOADED_DTB_BASE at build time.

Change-Id: I3206d6131059502ec96896e95329865452c9d83e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

The Statistical Profiling Extension (SPE) is an architectural feature we
can safely detect at runtime. However it still relies on one piece of
platform-specific information: the interrupt line it is connected
to. This requires SPE to be described in a devicetree node.

Since SPE support varies with the CPU cores found on an FPGA image, we
should detect the presence of SPE at runtime, and remove a potentially
existing SPE PMU node from the DT.

This allows to always have the SPE node in a generic devicetree file,
without risking exposing it on a CPU without this feature.

Change-Id: I73d83ea8509b03fe7bba20b9cce8d1335035fa31
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

The size of a GICv3 redistributor region depends on the number of
cores in the system. For the ARM FPGA port, we detect the topology at
runtime, and adjust the CPU DT nodes accordingly.
Now the size of the GICR region must also be adjusted, or Linux will
fail to initialise the GICv3.

Use the newly introduced function to overwrite the GICR size entry in
the GICv3 reg property. We count the number of existing cores by
iterating over the GICR frames until we find the LAST bit set in TYPER.

Change-Id: Ib69565600859de9b1b15ceb8495172cd26d16fce
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

We now have code to detect the CPU topology at runtime, and can also
populate the CPU nodes in a devicetree accordingly. This is used by the
ARM FPGA port, for instance.
But also a GICv3 compatible interrupt controller provides MMIO frames
per core, so the size of this region needs to be adjusted in the DT,
to match the number of cores as well.

Provide a generic function to find the GICv3 interrupt controller in
the DT, then adjust the "reg" entry to match the number of detected
cores. Since the size of the GICR frame per cores differs between
GICv4 and GICv3, this size is supplied as a parameter to the function.
The caller should determine the applicable value by either hardcoding
it or by observing GICR_TYPER.VLPIS.

Change-Id: Ic2a6445c2c5381a36bf24263f52fcbefad378c05
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

A GICv3 interrupt controller will be instantiated for a certain number
of cores. This will result in the respective number of GICR frames. The
last frame will have the "Last" bit set in its GICR_TYPER register.

For platforms with a topology unknown at build time (the Arm FPGAs, for
instance), we need to learn the number of used cores at runtime, to size
the GICR region in the devicetree accordingly.

Add a generic function that iterates over all GICR frames until it
encounters one with the "Last" bit set. It returns the number of cores
the GICv3 has been configured for.

Change-Id: I79f033c50dfc1c275aba7122725868811abcc4f8
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

* changes:
  plat/arm: Add platform support for Morello
  fdts: add device tree sources for morello platform
  lib/cpus: add support for Morello Rainier CPUs