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Add support to qemu "max" cpu for both "qemu" ('virt') and
"qemu_sbsa" ('sbsa-ref') platforms.

Change-Id: I36e45c0a3c4e30ba546d2a3cb44dfef11a680305
Signed-off-by: Leif Lindholm <leif@nuviainc.com>

Enable basic support for QEMU "max" CPU.
The "max" CPU does not attampt to emulate any specific CPU, but rather
just enables all the functions emulated by QEMU.

Change-Id: I69c212932ef61433509662d0fefbabb1e9e71cf2
Signed-off-by: Leif Lindholm <leif@nuviainc.com>

Cortex-A72 support is already enabled for sbsa-ref platform,
so add it also to virt platform for parity.

Change-Id: Ib0a2ce81ef7c0a71ef8dc66dbec179191bf2e6cc
Signed-off-by: Leif Lindholm <leif@nuviainc.com>

The build now gives deprecation warnings for including
drivers/arm/gic/common/gic_common.c directly. Move to including the
common gicv2 sources via gicv2.mk instead - which also matches the
pattern already used for gicv3.

Change-Id: I5332fb52c5801272e5e2bb6111f96087b4894325
Signed-off-by: Leif Lindholm <leif@nuviainc.com>

* changes:
  plat/st: do not keep mmc_device_info in stack
  plat/intel: do not keep mmc_device_info in stack
  plat/hisilicon: do not keep mmc_device_info in stack

* changes:
  mmc: remove useless extra semicolons
  Revert "mmc:prevent accessing to the released space in case of wrong usage"

Makefile for fiptool already prints verbose line when is (re)building
fiptool, so there is no need to print it also from top level Makefile.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I6936a508702f1bf796d17578bb1f043f06365319

Create a dedicated static struct mmc_device_info mmc_info mmc_info
instead of having this in stack.
A boot issue has been seen on some platform when applying patch [1].

 [1] 13f3c516

 ("mmc:prevent accessing to the released space in case of wrong usage")
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I73a079715253699d903721c865d6470d58f6bd30

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: If1d6b2040e482577292890e3554449096648c2ae

Create a dedicated static struct mmc_device_info mmc_info mmc_info
instead of having this in stack.
A boot issue has been seen on some platform when applying patch [1].

 [1] 13f3c516

 ("mmc:prevent accessing to the released space in case of wrong usage")
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Id52c0be61a30f453a551385883eaf3cbe32b04b9

This reverts commit 13f3c516

.
The STM32MP1 platform can no more boot qwith this change.
The driver will not be aware when the static struct in framework is updated.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Icc544e243136ee3b0067f316b71dff7dfd6526d6

Create a dedicated static struct mmc_device_info mmc_info mmc_info
instead of having this in stack.
A boot issue has been seen on some platform when applying patch [1].

 [1] 13f3c516

 ("mmc:prevent accessing to the released space in case of wrong usage")
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: If5db8857cccec2e677b16a38eb3eeb41628a264c

Calling 'make clean' in 'all' target is causing recompilation of binary
at every 'make' call, which is wrong.

Also building a new target via 'make TARGET' can cause infinite loop as
it is not defined as explicit make dependency. Dependent targets must be
specified after colon when defining target, which also prevents infinite
loops as make is able to detect these circular dependencies.

Moreover calling 'make clean' is supposed to be done by user when
configuration is changing.

So remove calling 'make clean' in 'all' target and define dependency for
'${PROJECT}' at correct place.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I70e7fd2b04b02f6a0650c82df91d58c9a4cb24d9

* changes:
  drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization
  drivers: marvell: comphy-a3700: Set mask parameter for every reg_set call
  drivers: marvell: comphy-a3700: Fix configuring polarity invert bits

* changes:
  plat: imx8mm: Add image load logic for TBBR FIP booting
  plat: imx8mm: Add initial defintions to facilitate FIP layout
  plat: imx8mm: Add image io-storage logic for TBBR FIP booting
  plat: imx8mm: Add imx8mm_private.h to the build

Since there is a secure and non-secure version of the timer registers
there is no need to preserve their context in EL3.
With that, following registers were removed from EL3 save/restore
routine:
	cnthps_ctl_el2
	cnthps_tval_el2
	cnthps_cval_el2
	cnthvs_ctl_el2
	cnthvs_tval_el2
	cnthvs_cval_el2
	cnthp_ctl_el2
	cnthp_cval_el2
	cnthp_tval_el2
	cnthv_ctl_el2
	cnthv_cval_el2
	cnthv_tval_el2
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: I6e2fc09c74a7375c4fccc11f12af4e39e6dc616b

* changes:
  plat/arm/arm_image_load: refine plat_add_sp_images_load_info
  plat/arm/arm_image_load: fix bug of overriding the last node

Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link
Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe
Root Complex mode. Both U-Boot and Linux kernel support only Root Complex
mode. Set this bit.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Id2a538c379b911b62597f9463b4842b7b5c24df7

The third argument of the reg_set() function has name 'mask', which
indicates that it is a mask applied to the register value which is
going to be updated. But the implementation of this function uses
this argument to clear prior value of the register, i.e. instead of
  new_val = (old_val & ~mask) | (data & mask);
it does
  new_val = (new_val & ~mask) | data;

(The more proper name for this function should be reg_clrsetbits(),
 since internally it calls mmio_clrsetbits_32().)

To make code more readable set 'mask' argument to real mask, i.e. bits
of register values which are going to be updated.

This patch does not make any functional change, only cosmetic, due to
how 'mask' is interpreted.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ifa0339e79c07d1994c7971b65d966b92cb735f65

TXD_INVERT_BIT or RXD_INVERT_BIT needs to be set only in case when
appropriate polarity is inverted. Otherwise these bits should be
cleared.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8b09fab883a7b995fd72a7d8ae6233f0fa07011b

Refine the function plat_add_sp_images_load_info() by saving the
previous node and only setting its next link when the current node is
valid. This can reduce the check for the next node and simply the
total logic.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I4061428bf49ef0c3816ac22aaeb2e50315531f88

The traverse flow in function plat_add_sp_images_load_info() will find
the last node in the main load info list, with its
next_load_info==NULL. However this node is still useful and should not
be overridden with SP node info.

The bug will cause below error on RDN2 for spmd enabled:

ERROR:   Invalid NT_FW_CONFIG DTB passed

Fix the bug by only setting the next_load_info of the last node in the
original main node list.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Icaee5da1f2d53b29fdd6085a8cc507446186fd57

Cortex A77 erratum 1946167 is a Cat B erratum that applies to revisions
<= r1p1. This erratum is avoided by inserting a DMB ST before acquire
atomic instructions without release semantics through a series of
writes to implementation defined system registers.

SDEN can be found here:
https://documentation-service.arm.com/static/600057a29b9c2d1bb22cd1be?token=

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I53e3b4fb7e7575ec83d75c2f132eda5ae0b4f01f

Add basic support for Cortex_A78C CPU.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Id9e41cbe0580a68c6412d194a5ee67940e8dae56

* changes:
  allwinner: H616: Add reserved-memory node to DT
  allwinner: Add Allwinner H616 SoC support
  allwinner: Add H616 SoC ID
  allwinner: Express memmap more dynamically
  allwinner: Move sunxi_cpu_power_off_self() into platforms
  allwinner: Move SEPARATE_NOBITS_REGION to platforms
  doc: allwinner: Reorder sections, document memory mapping

* changes:
  plat/sgi: allow usage of secure partions on rdn2 platform
  board/rdv1mc: initialize tzc400 controllers
  plat/sgi: allow access to TZC controller on all chips
  plat/sgi: define memory regions for multi-chip platforms
  plat/sgi: allow access to nor2 flash and system registers from s-el0
  plat/sgi: define default list of memory regions for dmc620 tzc
  plat/sgi: improve macros defining cper buffer memory region
  plat/sgi: refactor DMC-620 error handling SMC function id
  plat/sgi: refactor SDEI specific macros

Add the secure partition mmap table and the secure partition boot
information to support secure partitions on RD-N2 platform. In addition
to this, add the required memory region mapping for accessing the
SoC peripherals from the secure partition.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I2c75760d6c8c3da3ff4885599be420e924aeaf3c

* changes:
  stm32mp1: add TZC400 interrupt management
  stm32mp1: use TZC400 macro to describe filters
  tzc400: add support for interrupts

A TZC400 controller is placed inline on DRAM channels and regulates
the secure and non-secure accesses to both secure and non-secure
regions of the DRAM memory. Configure each of the TZC controllers
across the Chips.

For use by secure software, configure the first chip's trustzone
controller to protect the upper 16MB of the memory of the first DRAM
block for secure accesses only. The other regions are configured for
non-secure read write access. For all the remote chips, all the DRAM
regions are allowed for non-secure read and write access.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I809f27eccadfc23ea0ef64e2fd87f95eb8f195c1

On a multi-chip platform, the boot CPU on the first chip programs the
TZC controllers on all the remote chips. Define a memory region map for
the TZC controllers for all the remote chips and include it in the BL2
memory map table.

In addition to this, for SPM_MM enabled multi-chip platforms, increase
the number of mmap entries and xlat table counts for EL3 execution
context as well because the shared RAM regions and GIC address space of
remote chips are accessed.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I6f0b5fd22f9f28046451e382eef7f1f9258d88f7

For multi-chip platforms, add a macro to define the memory regions on
chip numbers >1 and its associated access permissions. These memory
regions are marked with non-secure access.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: If3d6180fd8ea61f45147c39d3140d694abf06617