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  1. 16 Jul, 2021 1 commit
    • Pali Rohár's avatar
      fix(plat/marvell/a3k): fix printing info messages on output · 9f6d1540
      Pali Rohár authored 
      

INFO() macro for every call prepends "INFO:   " string. Therefore
current code prints unreadable debug messages:

    "INFO:    set_io_addr_dec 0 result: ctrl(0x3fff3d01) base(0x0)INFO:    "
    "INFO:    Set IO decode window successfully, base(0xc000)INFO:     win_attr(3d) max_dram_win(2) max_remap(0)INFO:     win_offset(8)"

Fix it by calling exactly one INFO() call for one line. After this
change output is:

    "INFO:    set_io_addr_dec 0 result: ctrl(0x3fff3d01) base(0x0) remap(0x0)"
    "INFO:    Set IO decode window successfully, base(0xc000) win_attr(3d) max_dram_win(2) max_remap(0) win_offset(8)"
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I6084e64c6f4da6c1929e5300588e4ba2608ca745
      9f6d1540
  3. 08 Jul, 2021 2 commits
  5. 06 Jul, 2021 1 commit
  7. 05 Jul, 2021 1 commit
  9. 02 Jul, 2021 5 commits
  11. 30 Jun, 2021 2 commits
  13. 29 Jun, 2021 2 commits
    • Sandrine Bailleux's avatar
      refactor(plat/fvp): tidy up list of images to measure · 64dd1dee
      Sandrine Bailleux authored 
      

We don't ever expect to load a binary with an STM32 header on the Arm
FVP platform so remove this type of image from the list of
measurements.

Also remove the GPT image type from the list, as it does not get
measured. GPT is a container, just like FIP is. We don't measure the FIP
but rather the images inside it. It would seem logical to treat GPT the
same way.

Besides, only images that get loaded through load_auth_image() get
measured right now. GPT processing happens before that and is handled in
a different way (see partition_init()).

Change-Id: Iac4de75380ed625b228e69ee4564cf9e67e19336
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      64dd1dee
    • Manish Pandey's avatar
      feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1 · 7285fd5f
      Manish Pandey authored 
      For Arm platforms PIE is enabled when RESET_TO_BL31=1 in aarch64 mode on
the similar lines enable PIE when RESET_TO_SP_MIN=1 in aarch32 mode.
The underlying changes for enabling PIE in aarch32 is submitted in
commit 4324a14b

Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
Change-Id: Ib8bb860198b3f97cdc91005503a3184d63e15469
      7285fd5f
  15. 28 Jun, 2021 2 commits
  17. 25 Jun, 2021 2 commits
  19. 23 Jun, 2021 1 commit
    • Patrick Georgi's avatar
      fix(rockchip/rk3399): fix dram section placement · f943b7c8
      Patrick Georgi authored 
      

To quote jwerner in T925:
"The __sramdata in the declaration is a mistake, the correct target
section for that global needs to be .pmusram.data. This used to be
in .sram.data once upon a time but then the suspend.c stuff got added
and required it to be moved to PMUSRAM. I guess they forgot to update
that part in the declaration and since the old GCC seemed to silently
prefer the attribute in the definition, nobody noticed."

This fixes building with gcc 11.

fix #T925

Change-Id: I2b91542277c95cf487eaa1344927294d5d1b8f2b
Signed-off-by: default avatarPatrick Georgi <pgeorgi@google.com>
      f943b7c8
  21. 22 Jun, 2021 3 commits
  23. 17 Jun, 2021 2 commits
  25. 15 Jun, 2021 5 commits
  27. 14 Jun, 2021 1 commit
    • Michal Simek's avatar
      feat(plat/zynqmp): extend DT description by TF-A · 0a8143dd
      Michal Simek authored 
      

In case of TF-A running out of DDR there is a need to reserved
memory to let other SW know that none can't use this memory. HW
wise this region can be (and should be) also protected by
protection unit XMPU. This is the first step to add reserved
memory location to DT.

DT address corresponds with default address in U-Boot and also
default address in Xilinx BSPs.

Code is valid only when TF-A runs out of DDR. When it runs out
of OCM there is no need to reseve anything because OCM is hidden
to OS.

Change-Id: I01f230ced67207a159128cc11d11d36dd4590cab
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
      0a8143dd
  29. 12 Jun, 2021 2 commits
  31. 04 Jun, 2021 3 commits
  33. 03 Jun, 2021 5 commits