- 14 Sep, 2020 1 commit
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Sami Mujawar authored
Windows does not have a standard getopt implementation. To address this an equivalent implementation has been provided in win_posix.c However, the implementation has an issue with option processing as described below. Long option names may be abbreviated if the abbreviation is unique or an exact match for some defined option. Since some options can be substring of other options e.g. "scp-fw" option is a substring of "scp-fwu-cfg", we need to identify if an option is abbreviated and also check for uniqueness. Otherwise if a user passes --scp-fw as an option, the "scp-fwu-cfg" option may get selected, resulting in an incorrectly packaged FIP. This issue has been be fixed by: - First searching for an exact match. - If exact match was not found search for a abbreviated match. By doing this an incorrect option selection can be avoided. Change-Id: I22f4e7a683f3df857f5b6f0783bf9b03a64a0bcc Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
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- 10 Sep, 2020 4 commits
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Mark Dykes authored
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Manish Pandey authored
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Madhukar Pappireddy authored
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Anders Dellien authored
This fixes build errors for rdn1edge Change-Id: I63f7ebff68679e1e859f8786d4def4960c0f2ddf Signed-off-by: Anders Dellien <anders.dellien@arm.com>
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- 09 Sep, 2020 6 commits
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Mark Dykes authored
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Madhukar Pappireddy authored
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Manish Pandey authored
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Olivier Deprez authored
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Olivier Deprez authored
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Saurabh Gorecha authored
Follwing APIs wrappers are exposed to qtiseclib * strcmp * memset * memmove Change-Id: I79d50f358239cfda607d5f1a53314aa3b8f430cb Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
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- 08 Sep, 2020 2 commits
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Madhukar Pappireddy authored
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Avinash Mehta authored
This change replaces hdlcd with DPU in dts file for TC0 Change-Id: If25dfd3ddffc07279ab487f65e1bb82b27a26604 Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
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- 07 Sep, 2020 4 commits
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joanna.farley authored
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Max Shvetsov authored
spmd_get_context_by_mpidr was using potentially negative value as an array index. plat_core_pos_by_mpidr could return -1 on failure which is utilized by some platforms. Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: I7f8827e77f18da389c9cafdc1fc841aba9f03120
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Manish V Badarkhe authored
Coverity build periodically throws below errors(non-consistently) for 'QEMU' and 'RPI3' platforms. /bin/sh: 1: cannot create build/qemu/debug/rot_key.pem: Directory nonexistent plat/qemu/qemu/platform.mk:86: recipe for target 'build/qemu/debug/ rot_key.pem' failed make: *** [build/qemu/debug/rot_key.pem] Error 2 /bin/sh: 1: cannot create /work/workspace/workspace/tf-coverity/build /rpi3/debug/rot_key.pem: Directory nonexistent plat/rpi/rpi3/platform.mk:214: recipe for target '/work/workspace/ workspace/tf-coverity/build/rpi3/debug/rot_key.pem' failed make: *** [/work/workspace/workspace/tf-coverity/build/rpi3/debug/ rot_key.pem] Error 2 Issue seems to be occurred when 'ROT key' is generated before creating the platform build folder(for e.g.build/qemu/debug). Changes are made to fix this issue by adding orderly dependancy of the platform folder for the 'ROT key' creation which ensures that platform folder is created before generating 'ROT key'. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I20c82172dde84e4c7f2373c0bd095d353f845d38
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Manish V Badarkhe authored
This patch: fafd3ec9 assumes that tools must build from the main makefile folder. This assumption leads to the error when somebody wants to build a tool from the tool's folder. Hence changes are done to provide the default binary name in the tool's makefile. Change-Id: Iae570a7f8d322151376b6feb19e739300eecc3fc Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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- 03 Sep, 2020 6 commits
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Andre Przywara authored
Currently our memset() implementation is safe, but slow. The main reason for that seems to be the single byte writes that it issues, which can show horrible performance, depending on the implementation of the load/store subsystem. Improve the algorithm by trying to issue 64-bit writes. As this only works with aligned pointers, have a head and a tail section which covers unaligned pointers, and leave the bulk of the work to the middle section that does use 64-bit writes. Put through some unit tests, which exercise all combinations of nasty input parameters (pointers with various alignments, various odd and even sizes, corner cases of content to write (-1, 256)). Change-Id: I28ddd3d388cc4989030f1a70447581985368d5bb Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Manish Pandey authored
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Manish Pandey authored
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Madhukar Pappireddy authored
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Javier Almansa Sobrino authored
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I69365d4aed1160af41e291f6e4b1dd31cbd12e02
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Sandeep Tripathy authored
The API can be used to invoke a 'stop_func' callback for all other cores from any initiating core. Optionally it can also wait for other cores to power down. There may be various use of such API by platform. Ex: Platform may use this to power down all other cores from a crashed core. Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com> Change-Id: I4f9dc8a38d419f299c021535d5f1bcc6883106f9
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- 02 Sep, 2020 10 commits
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Madhukar Pappireddy authored
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Madhukar Pappireddy authored
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André Przywara authored
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Pramod Kumar authored
The DSU contains system control registers in the SCU and L3 logic to control the functionality of the cluster. If "DIRECT CONNECT" L3 memory system variant is used, there won't be any L3 cache, snoop filter, and SCU logic present hence no system control register will be present. Hence check SCU presence before accessing DSU register for DSU_936184 errata. Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com> Change-Id: I1ffa8afb0447ae3bd1032c9dd678d68021fe5a63
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Madhukar Pappireddy authored
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Javier Almansa Sobrino authored
At the moment BL31 dynamically discovers the CPU topology of an FPGA system at runtime, but does not export it to the non-secure world. Any BL33 user would typically looks at the devicetree to learn about existing CPUs. This patch exports a minimum /cpus node in a devicetree to satisfy the binding. This means that no cpumaps or caches are described. This could be added later if needed. An existing /cpus node in the DT will make the code bail out with a message. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I589a2b3412411a3660134bdcef3a65e8200e1d7e
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Anders Dellien authored
This patch adds dependencies to the generated configuration files that are included in the FIP. This fixes occasional build errors that occur when the FIP happens to be built first. Change-Id: I5a2bf724ba3aee13954403b141f2f19b4fd51d1b Signed-off-by: Anders Dellien <anders.dellien@arm.com>
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Manish Pandey authored
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Alexei Fedorov authored
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Alexei Fedorov authored
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- 01 Sep, 2020 7 commits
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Madhukar Pappireddy authored
* changes: Tegra: common: disable GICC after domain off cpus: denver: skip DCO enable/disable for recent SKUs
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Madhukar Pappireddy authored
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Mark Dykes authored
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Javier Almansa Sobrino authored
This patch creates and populates the /cpus node in a device tree based on the existing topology. It uses the minimum required nodes and properties to satisfy the binding as specified in https://www.kernel.org/doc/Documentation/devicetree/bindings/arm/cpus.txt Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I03bf4e9a6427da0a3b8ed013f93d7bc43b5c4df0
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Mark Dykes authored
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Mark Dykes authored
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Hsin-Yi Wang authored
Add jedec info for mt8173, mt8183, and mt8192. [1] http://www.softnology.biz/pdf/JEP106AV.pdf Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Change-Id: Iab36fd580131f0b09b27223fba0e9d1e187d9196
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