- 27 Mar, 2019 1 commit
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Paul Beesley authored
Change-Id: Ib6a20ffdddad11b9629d7dca7f841182299bf860 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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- 26 Mar, 2019 2 commits
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Ambroise Vincent authored
Make sure the steps in the user guide are up to date and can be performed out of the box. Change-Id: Ib4d959aa771cf515f74e150aaee2fbad24c18c38 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Paul Beesley authored
This is the temporary contents page that links to all other documents (except platform ports). This page is needed during the trustedfirmware.org migration, before we have a Sphinx rendering pipeline set up, because cgit doesn't offer a good way to view rendered docs while browsing the tree. We need to have a links page that can be opened from the cgit 'about' view. Change-Id: I3ad87a9fa8a14dc8e371aac7ee473575fed316bf Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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- 21 Mar, 2019 1 commit
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John Tsichritzis authored
Fixed the below bugs: 1) Bug related to build flag V=1: if the flag was V=0, building with ROMLIB would fail. 2) Due to a syntax bug in genwrappers.sh, index file entries marked as "patch" or "reserved" were ignored. 3) Added a prepending hash to constants that genwrappers is generating. 4) Due to broken dependencies, currently the inclusion functionality is intentionally not utilised. This is why the contents of romlib/jmptbl.i have been copied to platform specific jmptbl.i files. As a result of the broken dependencies, when changing the index files, e.g. patching functions, a clean build is always required. This is a known issue that will be fixed in the future. Change-Id: I9d92aa9724e86d8f90fcd3e9f66a27aa3cab7aaa Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 19 Mar, 2019 1 commit
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John Tsichritzis authored
Change-Id: I4261fec500184383980b7fc9475620a485cf6c28 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 18 Mar, 2019 1 commit
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Alexei Fedorov authored
Declare ENABLE_PAUTH and CTX_INCLUDE_PAUTH_REGS build options as experimental. Pointer Authentication is enabled for Non-secure world irrespective of the value of these build flags if the CPU supports it. The patch also fixes the description of fiptool 'help' command. Change-Id: I46de3228fbcce774a2624cd387798680d8504c38 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 14 Mar, 2019 1 commit
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John Tsichritzis authored
Change-Id: I1854b5830dbd48e909a4ce1b931c13fb3e997600 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 13 Mar, 2019 5 commits
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Ambroise Vincent authored
Change-Id: I3a101e540f0b134ecf9a51fa3d7d8e3d0369b297 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent authored
Change-Id: Ic3004fc43229d63c5a59ca74c1837fb0604e1f33 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent authored
This erratum can only be worked around on revisions >= r3p0 because the register that needs to be accessed only exists in those revisions[1]. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CIHEAAAD.html Change-Id: I5d773547d7a09b5bd01dabcd19ceeaf53c186faa Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent authored
Change-Id: I9755252725be25bfd0147839d7df56888424ff84 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Jacky Bai authored
The i.MX8M Mini is new SOC of the i.MX8M family. it is focused on delivering the latest and greatest video and audio experience combining state-of-the-art media-specific features with high-performance processing while optimized for lowest power consumption. The i.MX 8M Mini Media Applications Processor is 14nm FinFET product of the growing i.MX8M family targeting the consumer & industrial market. It is built in 14LPP to achieve both high performance and low power consumption and relies on a powerful fully coherent core complex based on a quad Cortex-A53 cluster with video and graphics accelerators this patch add the basic support for i.MX8MM. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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- 12 Mar, 2019 1 commit
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Alexei Fedorov authored
Change-Id: I56ea088f415bdb9077c385bd3450ff4b2cfa2eac Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 07 Mar, 2019 4 commits
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Paul Beesley authored
Some files imported from the wiki are missing RST section headers and other files are using inconsistent characters for the same header level. Change-Id: I318c843f9bc8fb40074ef90827b9acac06463662 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Paul Beesley authored
Some security advisories did not contain a direct link to the CVE page on mitre.org. Change-Id: I80f8f27a25da3a76b564a3e49cafe5e253379f37 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Joel Hutton authored
This patch covers two changes: - Links that refer to GitHub are updated to point to the relevant content on trustedfirmware.org - Internal links between documents have been updated, with the required .rst suffix being added or due to a change in the relative locations of the files. Change-Id: Ibf87da7d2ece726d1c94a9b33a2bbc3129de7779 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com> Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Joel Hutton authored
With the TF wiki being migrated from GitHub to trustedfirmware.org, some documents will be moved into the docs/ directory within the repository rather than remaining as external content. The appropriate action has been decided on a per-document basis. Change-Id: Id0f615f3418369256f30d2e34e354a115389d105 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com> Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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- 06 Mar, 2019 1 commit
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Paul Beesley authored
Keeping that in the docs is a bit untidy Change-Id: Ia95246208cee48df1536b4317a8c896ab2c84fc2 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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- 01 Mar, 2019 2 commits
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Sandrine Bailleux authored
Some of the sections numbers have been incorrect since the document structure has changed. Using references to sections rather than hard-coded section numbers fixes the issue while making it more future-proof to updates. Change-Id: I80f5ab6a55a0073b1562a02ce2c9ec7d67cddfff Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Sandrine Bailleux authored
While converting the interrupt framework design document from Markdown to reStructuredText format, see commit 6f625747 ("Convert documentation to reStructuredText"), the structure of the document was changed and one of the titles got lost. Fix that. Change-Id: Ib3e6c1f9f01f16108fde3b89ceb624bd54049d2f Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 28 Feb, 2019 10 commits
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Antonio Nino Diaz authored
Fix some typos and clarify some sentences. Change-Id: Id276d1ced9a991b4eddc5c47ad9a825e6b29ef74 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Louis Mayencourt authored
In AArch32, execution of 2 instructions with opposite condition code might lead to either a data corruption or a CPU deadlock. Set the bit 12 of the Diagnostic Register to prevent this. Change-Id: I22b4f25fe933e2942fd785e411e7c0aa39d5c1f4 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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Ambroise Vincent authored
The workarounds for these errata are so closely related that it is better to only have one patch to make it easier to understand. Change-Id: I0287fa69aefa8b72f884833f6ed0e7775ca834e9 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent authored
Change-Id: I25f29a275ecccd7d0c9d33906e6c85967caa767a Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent authored
Change-Id: Ice3dcba8c46cea070fd4ca3ffb32aedc840589ad Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent authored
Change-Id: I07e69061ba7a918cdfaaa83fa3a42dee910887d7 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent authored
Change-Id: Iacb6331c1f6b27340e71279f92f147ebbc71862f Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent authored
Change-Id: Ic42b37b8500d5e592af2b9fe130f35a0e2db4d14 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent authored
Change-Id: I094e5cb2c44618e7a4116af5fbb6b18078a79951 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent authored
Change-Id: Iebd45ef5e39ee7080235fb85414ce5b2e776f90c Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 27 Feb, 2019 3 commits
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Varun Wadekar authored
This patch provides support for using the scatterfile format as the linker script with the 'armlink' linker for Tegra platforms. In order to enable the scatterfile usage the following changes have been made: * provide mapping for ld.S symbols in bl_common.h * include bl_common.h from all the affected files * update the makefile rules to use the scatterfile and armlink to compile BL31 * update pubsub.h to add sections to the scatterfile NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY. Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Antonio Nino Diaz authored
The previous commit added the infrastructure to load and save ARMv8.3-PAuth registers during Non-secure <-> Secure world switches, but didn't actually enable pointer authentication in the firmware. This patch adds the functionality needed for platforms to provide authentication keys for the firmware, and a new option (ENABLE_PAUTH) to enable pointer authentication in the firmware itself. This option is disabled by default, and it requires CTX_INCLUDE_PAUTH_REGS to be enabled. Change-Id: I35127ec271e1198d43209044de39fa712ef202a5 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
ARMv8.3-PAuth adds functionality that supports address authentication of the contents of a register before that register is used as the target of an indirect branch, or as a load. This feature is supported only in AArch64 state. This feature is mandatory in ARMv8.3 implementations. This feature adds several registers to EL1. A new option called CTX_INCLUDE_PAUTH_REGS has been added to select if the TF needs to save them during Non-secure <-> Secure world switches. This option must be enabled if the hardware has the registers or the values will be leaked during world switches. To prevent leaks, this patch also disables pointer authentication in the Secure world if CTX_INCLUDE_PAUTH_REGS is 0. Any attempt to use it will be trapped in EL3. Change-Id: I27beba9907b9a86c6df1d0c5bf6180c972830855 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 26 Feb, 2019 7 commits
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Louis Mayencourt authored
Concurrent instruction TLB miss and mispredicted return instruction might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to prevent this. Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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Louis Mayencourt authored
Streaming store under specific conditions might cause deadlock or data corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write streaming to the L2 to prevent this. Change-Id: Ib5cabb997b35ada78b27e75787afd610ea606dcf Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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Louis Mayencourt authored
TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page aggregated address translation data in the L2 TLB might cause corruption of address translation data. Set bit 59 of CPUACTLR2_EL1 to prevent this. Change-Id: I59f3edea54e87d264e0794f5ca2a8c68a636e586 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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Louis Mayencourt authored
Internal timing conditions might cause the CPU to stop processing interrupts. Set bit 13 of CPUACTLR_EL1 to prevent this. Change-Id: Ifdd19dbcdb71bb0d9609cab1315c478aaedb03ba Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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Louis Mayencourt authored
Implicit Error Synchronization Barrier (IESB) might not be correctly generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all expection levels. Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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Louis Mayencourt authored
Broadcast maintainance operations might not be correctly synchronized between cores. Set bit 7 of S3_0_C15_C0_2 to prevent this. Change-Id: I67fb62c0b458d44320ebaedafcb8495ff26c814b Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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Tien Hock, Loh authored
This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A supports: - PSCI calls to enable 4 CPU cores - PSCI mailbox calls for FPGA reconfiguration Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
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