- 01 Mar, 2021 1 commit
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Masahisa Kojima authored
sbsa-ref in QEMU may create up to 512 cores. This commit prepares the MP information to support 512 cores. The number of xlat tables for spm_mm is also increased. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I2788eaf6d14e188e9b5d1102d359b2899e02df7c
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- 19 Jan, 2021 5 commits
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Graeme Gregory authored
This allows PSCI in TF-A to signal platform power states to QEMU via a controller in secure space. This required a sbsa-ref specific version of PSCI functions for the platform. Also adjusted the MMU range to also include the new EC. Add a new MMU region for the embedded controller and increase the size of xlat tables by one for the new region. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Change-Id: Iece8a88947f11e82ab8988e460a8a66ad175a5ee
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Graeme Gregory authored
sbsa-ref in QEMU creates clusers of 8 cores, it may create up to 512 cores in upto 64 clusters. Implement a qemu_sbsa specific topology file and increase the BL31_SIZE to accommodate the bigger table sizes. Change platform_def.h for new topology. Correct PLATFORM_CPU_PER_CLUSTER_SHIFT so plat_helpers.S calculates correct result. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Change-Id: Idc5d70394c0956b759ad2c86f9fda8f293f2cfa7
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Graeme Gregory authored
DEVICE2 is not currently used on qemu platform but is needed for a future patch for qemu_sbsa platform. Change its definition to RW and add it to all levels of arm-tf similar to DEVICE1 definition. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Change-Id: I03495471bfd423b61ad44ec4953fb25f76aa54bf
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Graeme Gregory authored
Rather than re-create this file in multiple qemu variants instead caclulate the shift needed to convert MPIDR to position. Add a new PLATFORM_CPU_PER_CLUSTER_SHIFT define in platform_def.h for both qemu and qemu_sbsa to enable this calculation. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Change-Id: I0e3a86354aa716d95150a3a34b15287cd70c8fd2
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Tomas Pilar authored
When getting a stack protector canary value, check if cpu supports FEAT_RNG and use that. Fallback to old method of using a (hardcoded value ^ timer). Signed-off-by: Tomas Pilar <tomas@nuviainc.com> Change-Id: I8181acf8e31661d4cc82bc3a4078f8751909e725
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- 13 Jan, 2021 1 commit
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Masahisa Kojima authored
This implements support for UEFI secure variable storage using standalone MM framework on qemu_sbsa platform. Non-secure shared memory between UEFI and standalone MM is allocated at the top of DRAM. DRAM size of qemu_sbsa varies depends on the QEMU parameter, so the non-secure shared memory is allocated by trusted firmware and passed the base address and size to UEFI through device tree "/reserved-memory" node. Change-Id: I367191f408eb9850b7ec7761ee346b014c539767 Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
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- 01 Dec, 2020 1 commit
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Masato Fukumori authored
Increase SHARED_RAM_SIZE in sbsa_qemu platform from 4KB to 8KB. sbsa_qemu uses SHARED_RAM for mail box and hold state of each cpus. If qemu is configured with 512 cpus, region size used by qemu is greater than 4KB. Signed-off-by: Masato Fukumori <masato.fukumori@linaro.org> Change-Id: I639e44e89335249d385cdc339350f509e9bd5e36
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- 20 Nov, 2020 1 commit
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Tanmay Jagdale authored
Include libraries needed to emulate Cortex-A72 on sbsa-ref target of QEMU. Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org> Change-Id: I98cf17b1662c70898977a841af07e07b5cfca8ba
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- 21 Oct, 2020 1 commit
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Tomas Pilar authored
The qemu_sbsa platform uses 42bit address size but the cortex-a53 only supports 40bit addressing, the cpu is incompatible with the platform. The aem_generic is also not used with qemu_sbsa, in fact, the platform currently only properly supports the cortex-a57 cpu. Change-Id: I91c92533116f1c3451d01ca99824e91d3d58df14 Signed-off-by: Tomas Pilar <tomas@nuviateam.com>
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- 09 Oct, 2020 1 commit
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Jimmy Brisson authored
And from crash_console_flush. We ignore the error information return by console_flush in _every_ place where we call it, and casting the return type to void does not work around the MISRA violation that this causes. Instead, we collect the error information from the driver (to avoid changing that API), and don't return it to the caller. Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
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- 07 Sep, 2020 1 commit
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Manish V Badarkhe authored
Coverity build periodically throws below errors(non-consistently) for 'QEMU' and 'RPI3' platforms. /bin/sh: 1: cannot create build/qemu/debug/rot_key.pem: Directory nonexistent plat/qemu/qemu/platform.mk:86: recipe for target 'build/qemu/debug/ rot_key.pem' failed make: *** [build/qemu/debug/rot_key.pem] Error 2 /bin/sh: 1: cannot create /work/workspace/workspace/tf-coverity/build /rpi3/debug/rot_key.pem: Directory nonexistent plat/rpi/rpi3/platform.mk:214: recipe for target '/work/workspace/ workspace/tf-coverity/build/rpi3/debug/rot_key.pem' failed make: *** [/work/workspace/workspace/tf-coverity/build/rpi3/debug/ rot_key.pem] Error 2 Issue seems to be occurred when 'ROT key' is generated before creating the platform build folder(for e.g.build/qemu/debug). Changes are made to fix this issue by adding orderly dependancy of the platform folder for the 'ROT key' creation which ensures that platform folder is created before generating 'ROT key'. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I20c82172dde84e4c7f2373c0bd095d353f845d38
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- 18 Aug, 2020 1 commit
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Masahisa Kojima authored
Enable the spm_mm framework for the qemu_sbsa platform. Memory layout required for spm_mm is created in secure SRAM. Co-developed-by: Fu Wei <fu.wei@linaro.org> Signed-off-by: Fu Wei <fu.wei@linaro.org> Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I104a623e8bc1e44d035b95f014a13b3f8b33a62a
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- 03 Jun, 2020 1 commit
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Masahisa Kojima authored
64KB was not enouth to handle fdt, bl2 shows following error message. "ERROR: Invalid Device Tree at 0x10000000000: error -3" This patch increases the size to 1MB to address above error. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I0726a0cea95087175451da0dba7410acd27df808
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- 19 May, 2020 1 commit
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Manish V Badarkhe authored
CoT used for BL1 and BL2 are moved to tbbr_cot_bl1.c and tbbr_cot_bl2.c respectively. Common CoT used across BL1 and BL2 are moved to tbbr_cot_common.c. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I2252ac8a6960b3431bcaafdb3ea4fb2d01b79cf5
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- 30 Mar, 2020 1 commit
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Alexei Fedorov authored
This patch moves all GICv3 driver files into new added 'gicv3.mk' makefile for the benefit of the generic driver which can evolve in the future without affecting platforms. The patch adds GICv3 driver configuration flags 'GICV3_IMPL', 'GICV3_IMPL_GIC600_MULTICHIP' and 'GICV3_OVERRIDE_DISTIF_PWR_OPS' described in 'GICv3 driver options' section of 'build-option.rst' document. NOTE: Platforms with GICv3 driver need to be modified to include 'drivers/arm/gic/v3/gicv3.mk' in their makefiles. Change-Id: If055f6770ff20f5dee5a3c99ae7ced7cdcac5c44 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 10 Mar, 2020 1 commit
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Alexei Fedorov authored
This patch provides separation of GICD, GICR accessor functions and adds new macros for GICv3 registers access as a preparation for GICv3.1 and GICv4 support. NOTE: Platforms need to modify to include both 'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the single helper file previously. Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 06 Mar, 2020 2 commits
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Sumit Garg authored
Enable encryption IO layer to be stacked above FIP IO layer for optional encryption of Bl31 and BL32 images in case ENCRYPT_BL31 or ENCRYPT_BL32 build flag is set. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I24cba64728861e833abffc3d5d9807599c49feb6
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Sumit Garg authored
Secure FLASH0 memory map looks like: - Offset: 0 to 256K -> bl1.bin - Offset: 256K to 4.25M -> fip.bin FLASH1 is normally used via UEFI/edk2 to keep varstore. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I6883f556c22d6a5d3fa3846c703bebc2abe36765
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- 25 Feb, 2020 1 commit
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I7a23327394d142af4b293ea7ccd90b843c54587c Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 07 Feb, 2020 1 commit
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Jerome Forissier authored
Commit 8f73663b ("plat/arm: Support for Cortex A5 in FVP Versatile Express platform") has conditioned the enabling of the Advanced SIMD and floating point features to platforms that have: (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_VFP) QEMU does support VFP so it should set ARMV7_SUPPORTS_VFP. Signed-off-by: Jerome Forissier <jerome@forissier.org> Change-Id: I3bab7c2ed04766d0628c14094557b2751f60a428
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- 29 Jan, 2020 1 commit
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Andrew Walbran authored
This is based on the rpi implementation from https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/2746 . Signed-off-by: Andrew Walbran <qwandor@google.com> Change-Id: I5fe324fcd9d5e232091e01267ea12147c46bc9c1
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- 24 Jan, 2020 1 commit
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I460b35f5a4ec47b13d4e811bb20881ce314e9259
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- 23 Jan, 2020 2 commits
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Andrew Walbran authored
This makes the PSCI SYSTEM_OFF call work on QEMU. It assumes that QEMU has semihosting enabled, but that is already assumed by the image loader. Signed-off-by: Andrew Walbran <qwandor@google.com> Change-Id: I0fb7cf7909262b675c3143efeac07f4d60730b03
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Andrew Walbran authored
This lets the Linux kernel or any other image which expects an FDT in x0 be loaded directly as BL33 without a separate bootloader on QEMU. Signed-off-by: Andrew Walbran <qwandor@google.com> Change-Id: Ia8eb4710a3d97cdd877af3b8aae36a2de7cfc654
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- 01 Oct, 2019 2 commits
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Radoslaw Biernacki authored
This patch adds mapping for secure FLASH0 for qemu/virt and qemu/qemu_sbsa platforms. This change is targeted for sbsa but since both platforms share common code, changes in common defines was necessary. For qemu_sbsa, this patch adds necessary mapping in order to boot without semi-hosting from secure FLASH0. EFI need to stay in FLASH1 (share it with variables) since it need to "run in place" in non secure domain. Changes for this are under RFC at edk2-platforms mailing list: https://patches.linaro.org/patch/171327/ (edk2-platforms/Platform/Qemu/SbsaQemu/SbsaQemu.dsc). In docs qemu/virt is described as using semi-hosting, therefore this change should be orthogonal to existing assumptions while giving possibility to store both bl1 and fip in FLASH0 at some point (additional changes required for that). Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Change-Id: I782bc3637c91c01eaee680b3c5c408e24b4b6e28
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Radoslaw Biernacki authored
This patch introduces Qemu SBSA platform. Both platform specific files where copied from qemu/qemu with changes for DRAM base above 32bit and removal of ARMv7 conditional defines/code. Documentation is aligned to rest of SBSA patches along the series and planed changes in edk2-platform repo. Fixes ARM-software/tf-issues#602 Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Change-Id: I8ebc34eedb2268365e479ef05654b2df1b99128c
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- 18 Sep, 2019 2 commits
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Radoslaw Biernacki authored
Patch introduce the macro NS_IMAGE_MAX_SIZE to simplify the image size calculation. Use of additional parenthesis removes the possibility of improper calculations due nested macro expansion for subtraction. In case of platforms with DRAM window over 32bits, patch also removes potential problems with type casting, as meminfo.image_size is uint32_t but macro calculations were done in 64bit space. Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Change-Id: I2d05a2d9dd6000dba6114df53262995cf85af018
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Radoslaw Biernacki authored
This commit change the plat/qemu directory structure into: `-- plat `-- qemu |-- common (files shared with all qemu subplatforms) |-- qemu (original qemu platform) |-- qemu_sbsa (new sqemu_sbsa platform) |-- subplat1 `-- subplat2 This opens the possibility of adding new qemu sub-platforms which reuse existing common platform code. The first platform which will leverage new structure will be SBSA platform. Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: Id0d8133e1fffc1b574b69aa2770ebc02bb837a9b
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- 13 Sep, 2019 1 commit
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Andre Przywara authored
The QEMU platform port scans its device tree to advertise PSCI as the CPU enable method. It does this by scanning *every* node in the DT and check whether its compatible string starts with "arm,cortex-a". Then it sets the enable-method to PSCI, if it doesn't already have one. Other platforms might want to use this functionality as well, so let's move it out of the QEMU platform directory and make it more robust by fixing some shortcomings: - A compatible string starting with a certain prefix is not a good way to find the CPU nodes. For instance a "arm,cortex-a72-pmu" node will match as well and is in turn favoured with an enable-method. - If the DT already has an enable-method, we won't change this to PSCI. Those two issues will for instance fail on the Raspberry Pi 4 DT. To fix those problems, we adjust the scanning method: The DT spec says that all CPU nodes are subnodes of the mandatory /cpus node, which is a subnode of the root node. Also each CPU node has to have a device_type = "cpu" property. So we find the /cpus node, then scan for a subnode with the proper device_type, forcing the enable-method to "psci". We have to restart this search after a property has been patched, as the node offsets might have changed meanwhile. This allows this routine to be reused for the Raspberry Pi 4 later. Change-Id: I00cae16cc923d9f8bb96a9b2a2933b9a79b06139 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 01 Aug, 2019 1 commit
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Julius Werner authored
NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__. All common C compilers pre-define the same macros to signal which architecture the code is being compiled for: __arm__ for AArch32 (or earlier versions) and __aarch64__ for AArch64. There's no need for TF-A to define its own custom macros for this. In order to unify code with the export headers (which use __aarch64__ to avoid another dependency), let's deprecate the AARCH32 and AARCH64 macros and switch the code base over to the pre-defined standard macro. (Since it is somewhat unintuitive that __arm__ only means AArch32, let's standardize on only using __aarch64__.) Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200 Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 26 Jul, 2019 2 commits
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Hongbo Zhang authored
This patch adds gicv3 support for qemu, in order not to break any legacy use case, gicv2 is still set by default, gicv3 can be selected by compiling parameter QEMU_USE_GIC_DRIVER=QEMU_GICV3. Signed-off-by: Hongbo Zhang <hongbo.zhang@linaro.org> Reviewed-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Tested-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Change-Id: Ic63f38abf16ed3c36aa60e80d50103cf05cf797b
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Hongbo Zhang authored
This file moves gicv2 codes to a new separate files, target is to add gicv3 support later. Signed-off-by: Hongbo Zhang <hongbo.zhang@linaro.org> Reviewed-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Tested-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Change-Id: I30eb1fda5ea5c2b35d79360c52f46601cbca1bcc
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- 28 Jun, 2019 2 commits
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Ambroise Vincent authored
Change-Id: Iab788e3e7cb2f83144255c4eb830712fd5cb6240 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent authored
The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 12 Apr, 2019 1 commit
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Ambroise Vincent authored
The implementation of the heap function plat_get_mbedtls_heap() becomes mandatory for platforms supporting TRUSTED_BOARD_BOOT. The shared Mbed TLS heap default weak function implementation is converted to a helper function get_mbedtls_heap_helper() which can be used by the platforms for their own function implementation. Change-Id: Ic8f2994e25e3d9fcd371a21ac459fdcafe07433e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 03 Apr, 2019 1 commit
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Ambroise Vincent authored
The default implementations are defined in crash_console_helpers.S. The platforms have to define plat_crash_console_*. Implemented placeholders for platforms that were missing helpers. Change-Id: Iea60b6f851956916e421dfd8c34a62d96eb9148e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 01 Feb, 2019 2 commits
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Antonio Nino Diaz authored
Also, update platform_def.h guidelines about includes in the porting guide. Change-Id: I1ae338c9dd3242b309f6d53687ba2cb755d488c3 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Many parts of the code were duplicating symbols that are defined in include/common/bl_common.h. It is better to only use the definitions in this header. As all the symbols refer to virtual addresses, they have to be uintptr_t, not unsigned long. This has also been fixed in bl_common.h. Change-Id: I204081af78326ced03fb05f69846f229d324c711 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 15 Jan, 2019 1 commit
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Antonio Nino Diaz authored
The definitions in bl1/bl1_private.h and bl2/bl2_private.h are useful for platforms that may need to access them. Change-Id: Ifd1880f855ddafcb3bfcaf1ed4a4e0f121eda174 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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