- 21 Sep, 2017 1 commit
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Sandrine Bailleux authored
platform_def.h doesn't need all the definitions in utils.h, the ones in utils_def.h are enough. This patch is related to the changes introduced by commit 53d9c9c8 . Change-Id: I4b2ff237a2d7fe07a7230e0e49b44b3fc2ca8abe Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 18 Sep, 2017 1 commit
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Soren Brinkmann authored
Synchronize argument order between function definition and declaration of pm_fpga_load. Fixes ARM-software/tf-issues#514 Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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- 13 Sep, 2017 2 commits
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Victor Chong authored
Otherwise, BL2 tries to load a BL32 image and triggers assert(result == 0) in plat_get_image_source() in hikey{960}_io_storage.c in a debug build, or displays ERROR: BL2: Failed to load image in a release build. Signed-off-by: Victor Chong <victor.chong@linaro.org>
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Victor Chong authored
Signed-off-by: Victor Chong <victor.chong@linaro.org>
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- 11 Sep, 2017 1 commit
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Soby Mathew authored
This patch gives users control over logging messages printed from the C code using the LOG macros defined in debug.h Users now have the ability to reduce the log_level at run time using the tf_log_set_max_level() function. The default prefix string can be defined by platform by overriding the `plat_log_get_prefix()` platform API which is also introduced in this patch. The new log framework results in saving of some RO data. For example, when BL1 is built for FVP with LOG_LEVEL=LOG_LEVEL_VERBOSE, resulted in saving 384 bytes of RO data and increase of 8 bytes of RW data. The framework also adds about 108 bytes of code to the release build of FVP. Fixes ARM-software/tf-issues#462 Change-Id: I476013d9c3deedfdd4c8b0b0f125665ba6250554 Co-authored-by: Eleanor Bonnici <Eleanor.bonnici@arm.com> Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 07 Sep, 2017 2 commits
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Eleanor Bonnici authored
Earlier patches added errata workarounds 859972 for Cortex-A72, and 859972 for Cortex-A57 CPUs. Explicitly disable the workaround for Juno. Also reorganize errata workaround flags. No functional changes. Change-Id: I3fe3745de57d77e5bf52012826d3969fe5d4844e Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Leo Yan authored
Every CPU has its own debug module and this module is used by JTAG debugging and coresight tracing. If without enabling it, it's easily to introduce lockup issue when we enable debugging features. This patch is to enable CPU debug module when power on CPU; this allows connecting to all cores through JTAG and used by kernel coresight driver. Signed-off-by: Matthias Welwarsky <maw@sysgo.com> Signed-off-by: Leo Yan <leo.yan@linaro.org>
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- 06 Sep, 2017 4 commits
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Soby Mathew authored
This patch does the required changes to enable CSS platforms to build and use the SDS framework. Since SDS is always coupled with SCMI protocol, the preexisting SCMI build flag is now renamed to `CSS_USE_SCMI_SDS_DRIVER` which will enable both SCMI and SDS on CSS platforms. Also some of the workarounds applied for SCMI are now removed with SDS in place. Change-Id: I94e8b93f05e3fe95e475c5501c25bec052588a9c Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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Soby Mathew authored
This patch introduces the driver for Shared-Data-Structure (SDS) framework which will be used for communication between SCP and AP CPU. The SDS framework is intended to replace the Boot-Over-MHU (BOM) protocol used currently for the communication Change-Id: Ic174291121f4e581b174cce3389d22d6435f7269 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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Soby Mathew authored
This patch factors out common files required for sp_min for all CSS platforms from the JUNO specific makefile to a the new `css_sp_min.mk` makefile. This also allows the common build options that affect CSS platforms to be configured in a central makefile for sp_min. Change-Id: Ida952d8833b1aa5eda77ae0a6664a4632aeab24c Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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Roberto Vargas authored
plat_get_my_entrypoint was branching to juno_do_reset_to_aarch_32_state, which is not supposed to return, and in case of returning it implemented an infinite loop. The problem was that plat_get_my_entrypoint was using "b" instead of "bl", so juno_do_reset_to_aarch_32_state was returning to the caller of plat_get_my_entrypoint instead of stop the system with a panic. To avoid this problem juno_do_reset_to_aarch_32_state was modified to call directly to plat_panic_handler if it tries to return. Change-Id: I591cf2dd78d27d8568fb15b91366e4b3dce027b5 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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- 05 Sep, 2017 1 commit
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Soby Mathew authored
The commit 3eb2d672 optimizes the memory map for BL2 when TSP is not present. But this also broke OP-TEE as it was reusing the TSP mapping. This patch fixes this problem by adding a separate mapping for OP-TEE in the BL2 memory map table. Change-Id: I130a2ea552b7b62d8478081feb1f4ddf5292a118 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 01 Sep, 2017 4 commits
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Victor Chong authored
Signed-off-by: Victor Chong <victor.chong@linaro.org>
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Victor Chong authored
Signed-off-by: Victor Chong <victor.chong@linaro.org> Signed-off-by: Leo Yan <leo.yan@linaro.org>
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Masahiro Yamada authored
Due to a bug in the Boot ROM, the USB load API turned out not working as expected. It is unfixable because the Boot ROM is hard-wired. Add work around code in TF to bypass the problematic Boot ROM code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
checkpatch.pl from Linux reports tons of coding style errors and warnings. I am just fixing under plat/socionext/uniphier/. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 31 Aug, 2017 3 commits
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Soby Mathew authored
The `KEY_ALG` variable is used to select the algorithm for key generation by `cert_create` tool for signing the certificates. This variable was previously undocumented and did not have a global default value. This patch corrects this and also adds changes to derive the value of `TF_MBEDTLS_KEY_ALG` based on `KEY_ALG` if it not set by the platform. The corresponding assignment of these variables are also now removed from the `arm_common.mk` makefile. Signed-off-by: Soby Mathew <soby.mathew@arm.com> Change-Id: I78e2d6f4fc04ed5ad35ce2266118afb63127a5a4
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Sandrine Bailleux authored
This patch ensures that the ARM_MAP_TSP_SEC_MEM memory region is mapped in BL2 only if the TSPD has been included in the build. This saves one entry in the plat_arm_mmap[] array and avoids to map extra memory when it's not needed. Change-Id: I6ae60822ff8f0de198145925b0b0d45355179a94 Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Soby Mathew authored
This patch fixes the PLAT_LOG_LEVEL_ASSERT to 40 which corresponds to LOG_LEVEL_INFO. Having this level of log for assertions means that the `assert()` will not generate the strings implied in the expression taken as parameter. This allows to save some memory when Juno is built for LOG_LEVEL = LOG_LEVEL_VERBOSE and DEBUG = 1. Fixes ARM-software/tf-issues#511 Change-Id: Id84a40f803ab07a5a8f6e587167af96694a07d04 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 30 Aug, 2017 1 commit
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Roberto Vargas authored
zero_normalmem only can zero memory when caches are enabled and the target memory is a normal memory, otherwise an abort is generated. In the case of EL3_PAYLOAD_BASE bl2_platform_setup was calling zero_normalmem with device memory and it generated an abort. Change-Id: If013603f209a12af488a9c54481f97a8f395b26a Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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- 29 Aug, 2017 11 commits
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Eleanor Bonnici authored
CORTEX_A57_ACTLR_EL1 macro refers to the CPUACTLR_EL1 register. Since ACTLR_EL1 is a different register (not implemented in Cortex-A57) this patch renames this macro for clarity. Change-Id: I94d7d564cd2423ae032bbdd59a99d2dc535cdff6 Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
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Eleanor Bonnici authored
Constants named as *ACTLR* refer in fact to the CPUACTRL_EL1 register. Since ACTLR and ACTRL_EL1 are different registers this patch renames these constants for clarity. Change-Id: I2a9e402dab7b0fcb6e481ee0d8a11eda943ed299 Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
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Jeenu Viswambharan authored
The current definition of ARM_INSTANTIATE_LOCK macro includes a semicolon, which means it's omitted where it's used. This is anomalous for a C statement in global scope. Fix this by removing semicolon from the definition; and where it's a NOP, declare a file-scoped variable explicitly tagged as unused to avoid compiler warning. No functional changes. Change-Id: I2c1d92ece4777e272a025011e03b8003f3543335 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Lin Huang authored
when shutdown logic power rail, the some sgrf register value will reset, so need to reinitilize secure. Change-Id: I8ad0570432e54441fe1c60dd2960a81fd58f7163 Signed-off-by: Lin Huang <hl@rock-chips.com>
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Lin Huang authored
we will use timer in pmusarm, when logic power rail shutdown, the secure timer will gone, so need to initial it in pmusram. Change-Id: I472e7eec3fc197f56223e6fff9167556c1c5e3bc Signed-off-by: Lin Huang <hl@rock-chips.com>
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Lin Huang authored
we do not have enough pmusram space now, so use slice1 to restore ddr slice1 ~ slice4, that's will save more pmusram space. Change-Id: Id54a7944f33d01a8f244cee6a8a0707bfe4d42da Signed-off-by: Lin Huang <hl@rock-chips.com>
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Lin Huang authored
Change-Id: Ia59adf48cf14eb627721264765bce50cb31065ef Signed-off-by: Lin Huang <hl@rock-chips.com>
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Lin Huang authored
pd_alive control cru, grf, timer, gpio and wdt, when turn off logic power rail, these register value will back to reset value, we need to save them value in suspend and restore them when resuem, since timer will reinitial in kernel, so it not need to save/restore. Change-Id: I0fc2a011d3cdc04b66ffbf728e769eb28b51ee38 Signed-off-by: Lin Huang <hl@rock-chips.com>
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Leo Yan authored
At the system boot time we need enable watchdog reset, otherwise after the watchdog is timeout it cannot reset the SoC. We need set the bit 0 and bit 16 together, the bit 16 is mask bit so after set bit 16 we have permission to operate bit 0 and bit 0 is watchdog reset enabling bit. Signed-off-by: Leo Yan <leo.yan@linaro.org>
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Lin Huang authored
when logic power rail shutdown, CRU register will back to reset value, ddr use abpll as clock source when do suspend, we need to save and dpll value in pmusram, then set back these ddr clock back to dpll when dddr resume. Change-Id: I95dc0173649e8515859cfa46b40a606e0cc2fe3f Signed-off-by: Lin Huang <hl@rock-chips.com>
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Lin Huang authored
when shutdown logic power rail, the uart register value will reset, so need to reinitilize debug uart. Change-Id: I48d3535c0068fd671dea6ea32e908612992faf62 Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
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- 25 Aug, 2017 1 commit
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Jens Wiklander authored
If SPD_opteed is defined map ARM_OPTEE_PAGEABLE_LOAD_MEM in bl2 to allow loading of OP-TEE paged part. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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- 24 Aug, 2017 3 commits
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Jens Wiklander authored
OP-TEE may have extra images to be loaded. Load them one by one and do the parsing. In this patch, ARM TF need to load up to 3 images for OP-TEE: header, pager and pages images. Header image is the info about optee os and images. Pager image include pager code and data. Paged image include the paging parts using virtual memory. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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Jens Wiklander authored
Change to compile with new plat/common/plat_psci_common.c instead of the old deprecated plat/common/aarch64/plat_psci_common.c Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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Jens Wiklander authored
Replaces the deprecated ADDR_SPACE_SIZE with PLAT_PHY_ADDR_SPACE_SIZE and PLAT_VIRT_ADDR_SPACE_SIZE. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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- 23 Aug, 2017 2 commits
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Isla Mitchell authored
At present, the MPIDR validation on FVP relies on MT bit set along with shifted affinities. This currently is additionally dependent on the FVP model being of variant C. This however should be based on the presence of MT bit alone. This patch makes the change to always assume that the affinities are shifted in the FVP model when MT bit is present. Change-Id: I09fcb0126e1b38d29124bdeaf3450a60b95d485d Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
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Roberto Vargas authored
The nor_XXXXX functions may fail due to different reasons, and it is convenient to do a full check to detect any failure. It is also a good idea to have a specific function to do a full status check, because new checks can be added to this function and they will be incorporated automatically to any function calling it. Change-Id: I54fed913e37ef574c1608e94139a519426348d12 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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- 22 Aug, 2017 3 commits
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Roberto Vargas authored
NOR memory only supports setting bits to 1. To clear a bit, set to zero, the NOR memory needs to be erased. Change-Id: Ia82eb15a5af9a6d4fc7e5ea2b58e6db87226b351 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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Roberto Vargas authored
The status register bits remain until explicitly cleared, which means that a command can be incorrectly considered to have generated an error - for example, after reset the status register contents may be unknown or if a previous command had failed. This patch clears the status register before beginning any command to be sure that the status register only represents information about the current operation. Change-Id: I9e98110ee24179937215461c00b6543a3467b350 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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Roberto Vargas authored
lock/unlock operation must wait until WSM bit is set. Since we do not allow to loop forever then these functions must return an error if WSM bit isn't enabled after a number of tries. Change-Id: I21c9e292b514b28786ff4a225128bcd8c1bfa999 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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