- 20 Oct, 2020 1 commit
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Arunachalam Ganapathy authored
Statistical Profiling Extension is not supported by Matterhorn core Change-Id: Iec652f1c6d6b6a9bf118ba682276a7c70a6abc0d Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
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- 24 Sep, 2020 1 commit
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Usama Arif authored
Change-Id: Ic2bb8482f0b602f6b7850d4fa553448bc4931edc Signed-off-by: Usama Arif <usama.arif@arm.com>
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- 10 Sep, 2020 1 commit
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Usama Arif authored
The size of debug binaries of SCP has increased beyond the current limit of 80kB set in platform. Hence, increase it to 128kB. Change-Id: I5dbcf87f8fb35672b39abdb942c0691fb339444a Signed-off-by: Usama Arif <usama.arif@arm.com>
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- 02 Sep, 2020 1 commit
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Anders Dellien authored
This patch adds dependencies to the generated configuration files that are included in the FIP. This fixes occasional build errors that occur when the FIP happens to be built first. Change-Id: I5a2bf724ba3aee13954403b141f2f19b4fd51d1b Signed-off-by: Anders Dellien <anders.dellien@arm.com>
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- 14 Aug, 2020 1 commit
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Jimmy Brisson authored
This resolves MISRA defects such as: plat/common/plat_bl1_common.c:63:[MISRA C-2012 Rule 14.4 (required)] The condition expression "1" does not have an essentially boolean type. Change-Id: I679411980ad661191fbc834a44a5eca5494fd0e2 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
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- 31 Jul, 2020 1 commit
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Olivier Deprez authored
Following merge of patchset [1] the spm_mm_boot_info_t structure is included in few platform files unconditionally even when SPM_MM option is disabled. [1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/2647 Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I68bc034c9348b5d9bcfd2e5217b781df5ad1b369
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- 24 Jun, 2020 1 commit
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Manish V Badarkhe authored
Moved BL2 configuration nodes from fw_config to newly created tb_fw_config device tree. fw_config device tree's main usage is to hold properties shared across all BLx images. An example is the "dtb-registry" node, which contains the information about the other device tree configurations (load-address, size). Also, Updated load-address of tb_fw_config which is now located after fw_config in SRAM. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ic398c86a4d822dacd55b5e25fd41d4fe3888d79a
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- 17 Jun, 2020 1 commit
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Manish V Badarkhe authored
Load address of tb_fw_config is incorrectly mentioned in below device trees: 1. rdn1edge_fw_config.dts 2. tc0_fw_config.dts Till now, tb_fw_config load-address is not being retrieved from device tree and hence never exeprienced any issue for tc0 and rdn1edge platform. For tc0 and rdn1edge platform, Load-address of tb_fw_config should be the SRAM base address + 0x300 (size of fw_config device tree) Hence updated these platform's fw_config.dts accordingly to reflect this load address change. Change-Id: I2ef8b05d49be10767db31384329f516df11ca817 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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- 09 Jun, 2020 1 commit
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Andre Przywara authored
The only difference between GIC-500 and GIC-600 relevant to TF-A is the differing power management sequence. A certain GIC implementation is detectable at runtime, for instance by checking the IIDR register. Let's add that test before initiating the GIC-600 specific sequence, so the code can be used on both GIC-600 and GIC-500 chips alike, without deciding on a GIC chip at compile time. This means that the GIC-500 "driver" is now redundant. To allow minimal platform support, add a switch to disable GIC-600 support. Change-Id: I17ea97d9fb05874772ebaa13e6678b4ba3415557 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 08 Jun, 2020 1 commit
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Manish Pandey authored
As per "include/export/README", TF-A code should never include export headers directly. Instead, it should include a wrapper header that ensures the export header is included in the right manner. "tbbr_img_def_exp.h" is directly included in TF-A code, this patch replaces it with its wrapper header "tbbr_img_def.h". Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I31c1a42e6a7bcac4c396bb17e8548567ecd8147d
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- 27 May, 2020 1 commit
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Usama Arif authored
This patch adds support for Total Compute (TC0) platform. It is an initial port and additional features are expected to be added later. TC0 has a SCP which brings the primary Cortex-A out of reset which starts executing BL1. TF-A optionally authenticates the SCP ram-fw available in FIP and makes it available for SCP to copy. Some of the major features included and tested in this platform port include TBBR, PSCI, MHUv2 and DVFS. Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef Signed-off-by: Usama Arif <usama.arif@arm.com>
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