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  1. 25 Nov, 2019 2 commits
  3. 19 Nov, 2019 1 commit
  5. 18 Nov, 2019 1 commit
    • Louis Mayencourt's avatar
      ROMLIB: Optimize memory layout when ROMLIB is used · e7b39089
      Louis Mayencourt authored 
      

ROMLIB extract functions code from BL images to put them inside ROM.
This has for effect to reduce the size of the BL images.

This patch take this size reduction into consideration to optimize the
memory layout of BL2.
A new "PLAT_ARM_BL2_ROMLIB_OPTIMIZATION" macro is defined and used to
reduce "PLAT_ARM_MAX_BL2_SIZE". This allows to remove the gap between
BL1 and BL2 when ROMLIB is used and provides more room for BL31.

The current memory gain is 0x6000 for fvp and 0x8000 for juno.

Change-Id: I71c2c2c63b57bce5b22a125efaefc486ff3e87be
Signed-off-by: default avatarLouis Mayencourt <louis.mayencourt@arm.com>
      e7b39089
  7. 15 Nov, 2019 1 commit
  9. 13 Nov, 2019 7 commits
  11. 11 Nov, 2019 1 commit
    • Manish Pandey's avatar
      n1sdp: setup multichip gic routing table · 6799a370
      Manish Pandey authored 
      

N1SDP supports multichip configuration wherein n1sdp boards are
connected over high speed coherent CCIX link, for now only dual-chip
is supported.

Whether or not multiple chips are present is dynamically probed by
SCP firmware and passed on to TF-A, routing table will be set up
only if multiple chips are present.

Initialize GIC-600 multichip operation by overriding the default GICR
frames with array of GICR frames and setting the chip 0 as routing
table owner.

Change-Id: Ida35672be4bbf4c517469a5b330548d75e593ff2
Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
      6799a370
  13. 07 Nov, 2019 1 commit
  15. 05 Nov, 2019 2 commits
  17. 31 Oct, 2019 1 commit
    • Manish Pandey's avatar
      n1sdp: update platform macros for dual-chip setup · f91a8e4c
      Manish Pandey authored 
      

N1SDP supports multichip configuration wherein n1sdp boards are
connected over high speed coherent CCIX link  for now only dual-chip is
supported.

A single instance of TF-A runs on master chip which should be aware of
slave chip's CPU and memory topology.

This patch updates platform macros to include remote chip's information
and also ensures that a single version of firmware works for both single
and dual-chip setup.

Change-Id: I75799fd46dc10527aa99585226099d836c21da70
Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
      f91a8e4c
  19. 30 Oct, 2019 1 commit
    • Manish Pandey's avatar
      n1sdp: introduce platform information SDS region · 34c7af41
      Manish Pandey authored 
      

Platform information structure holds information about platform's DDR
size(local/remote) which will be used to zero out the memory before
enabling the ECC capability as well as information about multichip
setup. Multichip and remote DDR information can only be probed in SCP,
SDS region will be used by TF-A to get this information at boot up.

This patch introduces a new SDS to store platform information, which is
populated dynamically by SCP Firmware.previously used mem_info SDS is
also made part of this structure itself.

The platform information is also passed to BL33 by copying it to Non-
Secure SRAM.

Change-Id: I4781dc6a7232c3c0a3219b164d943ce9e3e469ee
Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
      34c7af41
  21. 29 Oct, 2019 1 commit
    • Andrew F. Davis's avatar
      ti: k3: common: Add PIE support · ff835a9a
      Andrew F. Davis authored 
      

Running TF-A from non-standard location such as DRAM is useful for some
SRAM heavy use-cases. Allow the TF-A binary to be executed from an
arbitrary memory location.
Signed-off-by: default avatarAndrew F. Davis <afd@ti.com>
Change-Id: Icd97926e4d97f37d7cde4a92758a52f57d569111
      ff835a9a
  23. 24 Oct, 2019 13 commits
  25. 21 Oct, 2019 1 commit
    • Manish Pandey's avatar
      plat/arm: use Aff3 bits also to validate mpidr · b30646a8
      Manish Pandey authored 
      

There are some platforms which uses MPIDR Affinity level 3 for storing
extra affinity information e.g. N1SDP uses it for keeping chip id in a
multichip setup, for such platforms MPIDR validation should not fail.

This patch adds Aff3 bits also as part of mpidr validation mask, for
platforms which does not uses Aff3 will not have any impact as these
bits will be all zeros.

Change-Id: Ia8273972fa7948fdb11708308d0239d2dc4dfa85
Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
      b30646a8
  27. 03 Oct, 2019 5 commits
  29. 02 Oct, 2019 1 commit
  31. 01 Oct, 2019 1 commit
    • Radoslaw Biernacki's avatar
      qemu/qemu_sbsa: Adding memory mapping for both FLASH0/FLASH1 · fa405e3b
      Radoslaw Biernacki authored 
      This patch adds mapping for secure FLASH0 for qemu/virt and
qemu/qemu_sbsa platforms. This change is targeted for sbsa but since both
platforms share common code, changes in common defines was necessary.

For qemu_sbsa, this patch adds necessary mapping in order to boot without
semi-hosting from secure FLASH0. EFI need to stay in FLASH1 (share it with
variables) since it need to "run in place" in non secure domain. Changes
for this are under RFC at edk2-platforms mailing list:
https://patches.linaro.org/patch/171327/


(edk2-platforms/Platform/Qemu/SbsaQemu/SbsaQemu.dsc).

In docs qemu/virt is described as using semi-hosting, therefore this change
should be orthogonal to existing assumptions while giving possibility to
store both bl1 and fip in FLASH0 at some point (additional changes required
for that).
Signed-off-by: default avatarRadoslaw Biernacki <radoslaw.biernacki@linaro.org>
Change-Id: I782bc3637c91c01eaee680b3c5c408e24b4b6e28
      fa405e3b