- 01 Aug, 2019 1 commit
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Julius Werner authored
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__. All common C compilers predefine a macro called __ASSEMBLER__ when preprocessing a .S file. There is no reason for TF-A to define it's own __ASSEMBLY__ macro for this purpose instead. To unify code with the export headers (which use __ASSEMBLER__ to avoid one extra dependency), let's deprecate __ASSEMBLY__ and switch the code base over to the predefined standard. Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417 Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 28 Jun, 2019 1 commit
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Ambroise Vincent authored
The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 26 Jun, 2019 1 commit
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Ambroise Vincent authored
This interface has been deprecated in favour of MULTI_CONSOLE_API. Change-Id: I6170c1c8c74a890e5bd6d05396743fe62024a08a Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 05 Jun, 2019 1 commit
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James kung authored
According to Arm GIC spec(IHI0069E, section 4.6.1), when GICD_CTLR.DS == 0, Secure Group 1 interrupts are treated as Group 0 by a CPU interface if: - The PE does not implement EL3. - ICC_SRE_EL1(S).SRE == 0 When a cpu enter suspend or deep idle, it might be powered off. When the cpu resume, according to the GIC spec(IHI0069E, section 9.2.15, 9.2.16 and 9.2.22) the ICC_SRE_EL1.SRE reset value is 0 (if write is allowed) and G0/G1S/G1NS interrupt of the GIC cpu interface are all disabled. If a G1S SPI interrupt occurred and the target cpu of the SPI is assigned to a specific cpu which is in suspend and is powered off, when the cpu resume and start to initial the GIC cpu interface, the initial sequence might affect the interrupt group type of the pending interrupt on the cpu interface. Current initial sequence on the cpu interface is: 1. Enable G0 interrupt 2. Enable G1S interrupt 3. Enable ICC_SRE_EL1(S).SRE It is possible to treat the pending G1S interrupt as G0 interrupt on the cpu interface if the G1S SPI interrupt occurred between step2 and step3. To prevent the above situation happend, the initial sequence should be changed as follows: 1. Enable ICC_SRE_EL1(S).SRE 2. Enable G0 interrupt 3. Enable G1S interrupt Change-Id: Ie34f6e0b32eb9a1677ff72571fd4bfdb5cae25b0 Signed-off-by: James Kung <kong1191@gmail.com>
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- 23 May, 2019 1 commit
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Masahisa Kojima authored
Payload length of the get dram mapping information message is 0. The mbx_mem->len parameter should be 4, it only contains message header. Fixes: b67d2029 ("plat/synquacer: enable SCMI support") Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: If1cd4c855da2dc5dc4b6da3bea152b8441971de7
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- 10 May, 2019 1 commit
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Alexei Fedorov authored
For security DMA should be blocked at the SMMU by default unless explicitly enabled for a device. SMMU is disabled after reset with all streams bypassing the SMMU, and abortion of all incoming transactions implements a default deny policy on reset. This patch also moves "bl1_platform_setup()" function from arm_bl1_setup.c to FVP platforms' fvp_bl1_setup.c and fvp_ve_bl1_setup.c files. Change-Id: Ie0ffedc10219b1b884eb8af625bd4b6753749b1a Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 03 May, 2019 1 commit
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Alexei Fedorov authored
This patch is a preparation for the subsequent changes in SMMUv3 driver. It introduces a new "smmuv3_poll" function and replaces inline functions for accessing SMMU registers with mmio read/write operations. Also the infinite loop for the poll has been replaced with a counter based timeout. Change-Id: I7a0547beb1509601f253e126b1a7a6ab3b0307e7 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 17 Apr, 2019 1 commit
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Aditya Angadi authored
Add a driver for configuring the SBSA Generic Watchdog which aids in the detection of errant system behaviour. Change-Id: I5a1e7149c69fd8b85be7dfbcf511f431339946f4 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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- 03 Apr, 2019 2 commits
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Ambroise Vincent authored
Types tzc_action_t and tzc_region_attributes_t are deprecated. Change-Id: Ieefeb8521a0e1130f39d09b5c0d2728f05084773 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Ambroise Vincent authored
The old version of the macro is deprecated. Commit cc5859ca ("Multi-console: Deprecate the `finish_console_register` macro") provides more details. Change-Id: I3d1cdf6496db7d8e6cfbb5804f508ff46ae7e67e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 01 Apr, 2019 1 commit
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Ambroise Vincent authored
Improved support for W=2 compilation flag by solving some nested-extern and sign-compare warnings. The libraries are compiling with warnings (which turn into errors with the Werror flag). Outside of libraries, some warnings cannot be fixed. Change-Id: I06b1923857f2a6a50e93d62d0274915b268cef05 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 13 Mar, 2019 1 commit
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Masahisa Kojima authored
Enable the SCMI protocol support in SynQuacer platform. Aside from power domain, system power and apcore management protocol, this commit adds the vendor specific protocol(0x80). This vendor specific protocol is used to get the dram mapping information from SCP. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
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- 28 Feb, 2019 1 commit
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Antonio Nino Diaz authored
Fix some typos and clarify some sentences. Change-Id: Id276d1ced9a991b4eddc5c47ad9a825e6b29ef74 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 19 Feb, 2019 1 commit
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Usama Arif authored
Cortex a5 doesnt support hardware division such as sdiv and udiv commands. This commit adds a software division function in assembly as well as include appropriate files for software divison. The software division algorithm is a modified version obtained from: http://www.keil.com/support/man/docs/armasm/armasm_dom1359731155623.htm Change-Id: Ib405a330da5f1cea1e68e07e7b520edeef9e2652 Signed-off-by: Usama Arif <usama.arif@arm.com>
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- 04 Feb, 2019 1 commit
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Soby Mathew authored
Previously the GICv3 redistributor probe function (gicv3_rdistif_base_addrs_probe()) asserted that the number of per-CPU redistributor interfaces expected to be probed by the platform is equal to the number exported by the redistributor frame. This is a problem in case the number of CPUs in the platform is less than the number of redistributor interfaces in the frame. Hence this patch removes the assertion check and allows probe for fewer redistributor interfaces as required by the platform. Change-Id: I3449763a3ad70817224442cbe184d001030c9874 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 25 Jan, 2019 6 commits
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Antonio Nino Diaz authored
Change-Id: I670ea80e0331c2d4b2ccfa563a45469a43f6902d Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: Ia601d5ad65ab199e747fb60af4979b7db477d249 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: Ida5dae39478654405d0ee31a6cbddb4579e76a7f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: Icc59cdaf2b56f6936e9847f1894594c671db2e94 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: I656753a1825ea7340a3708b950fa6b57455e9056 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: I8989d2aa0258bf3b50a856c5b81532d578600124 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 15 Jan, 2019 1 commit
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Paul Beesley authored
Corrects typos in core code, documentation files, drivers, Arm platforms and services. None of the corrections affect code; changes are limited to comments and other documentation. Change-Id: I5c1027b06ef149864f315ccc0ea473e2a16bfd1d Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 12 Dec, 2018 1 commit
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Pankaj Gupta authored
For RN-I, node id is used instead of node postion in the bitmap to calculate the region id. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
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- 07 Dec, 2018 1 commit
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Julius Werner authored
This patch makes the build system link the console framework code by default, like it already does with other common libraries (e.g. cache helpers). This should not make a difference in practice since TF is linked with --gc-sections, so the linker will garbage collect all functions and data that are not referenced by any other code. Thus, if a platform doesn't want to include console code for size reasons and doesn't make any references to console functions, the code will not be included in the final binary. To avoid compatibility issues with older platform ports, only make this change for the MULTI_CONSOLE_API. Change-Id: I153a9dbe680d57aadb860d1c829759ba701130d3 Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 05 Dec, 2018 1 commit
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Antonio Nino Diaz authored
This driver can be compiled in release builds, but GCC generates warnings for some comparisons and that prevents the firmware from being built in debug builds. Change-Id: Ic52e1b4a11896ecf086864fbe2b5bfc143ec9b1b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 04 Dec, 2018 1 commit
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Peng Fan authored
Add tzc380 support. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
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- 23 Nov, 2018 1 commit
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Pankaj Gupta authored
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
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- 21 Nov, 2018 1 commit
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Vijayenthiran Subramaniam authored
ARM CoreLink DMC-620 Dynamic Memory Controller includes a TZC controller to setup secure or non-secure regions of DRAM memory. The TZC controller allows to setup upto eight such regions of memory in DRAM. This driver provides helper functions to setup the TZC controller within DMC-620. Change-Id: Iee7692417c2080052bdb7b1c2873a024bc5d1d10 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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- 08 Nov, 2018 1 commit
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Antonio Nino Diaz authored
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 06 Nov, 2018 1 commit
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Sandrine Bailleux authored
This function was needed at the time where we didn't have the compiler_rt lib. An AArch32-specific variant was provided to handle the 64-bit shift operation in 32-bit. This is no longer needed. Change-Id: Ibab709a95e3a723ae2eeaddf873dba70ff2012b3 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 23 Oct, 2018 1 commit
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Antonio Nino Diaz authored
The definitions FAIL_CONTROL_*_SHIFT were incorrect, they have been fixed. The types tzc_region_attributes_t and tzc_action_t have been removed and replaced by unsigned int because it is not allowed to do logical operations on enums. Also, fix some address definitions in arm_def.h. Change-Id: Id37941d76883f9fe5045a5f0a4224c133c504d8b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 19 Oct, 2018 1 commit
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Soby Mathew authored
The `finish_console_register` macro is used by the multi console framework to register the `console_t` driver callbacks. It relied on weak references to the `ldr` instruction to populate 0 to the callback in case the driver has not defined the appropriate function. Use of `ldr` instruction to load absolute address to a reference makes the binary position dependant. These instructions should be replaced with adrp/adr instruction for position independant executable(PIE). But adrp/adr instructions don't work well with weak references as described in GNU ld bugzilla issue 22589. This patch defines a new version of `finish_console_register` macro which can spcify which driver callbacks are valid and deprecates the old one. If any of the argument is not specified, then the macro populates 0 for that callback. Hence the functionality of the previous deprecated macro is preserved. The USE_FINISH_CONSOLE_REG_2 define is used to select the new variant of the macro and will be removed once the deprecated variant is removed. All the upstream console drivers have been migrated to use the new macro in this patch. NOTE: Platforms be aware that the new variant of the `finish_console_register` should be used and the old variant is deprecated. Change-Id: Ia6a67aaf2aa3ba93932992d683587bbd0ad25259 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 12 Oct, 2018 1 commit
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Antonio Nino Diaz authored
The comments with the prototypes of the register functions of the console drivers are incorrect. The arguments are wrong. This patch fixes them. Change-Id: I38c4b481ee69e840780111c42f03c0752eb6315c Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 03 Oct, 2018 1 commit
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Daniel Boulby authored
Mark the GICv3, CCI and CCN code only used in Bl31 initialization with __init to be reclaimed once no longer needed. Change-Id: I3d77f36758450d9d1d87ecc60bc1c63fe4082667 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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- 28 Sep, 2018 4 commits
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Antonio Nino Diaz authored
Change-Id: Ib9eebbdff6f7868e1d1b8c41761cacc7501a25bd Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
This driver is deprecated. Change-Id: Ic6e154a5756e779743b17a329eed4570ccc61389 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: I9874883ec33dbf293f607f9779d7c56f23cb8023 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: I567a406edb090ae9d109382f6874846a79dd7473 Co-authored-by: Roberto Vargas <roberto.vargas@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 21 Sep, 2018 1 commit
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Daniel Boulby authored
Allow AArch32 to use the multi console driver by adding the required functions Change-Id: I9e69f18965f320074cf75442d6b0de891aef7936 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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