1. 09 Feb, 2016 3 commits
    • Soby Mathew's avatar
      Move private APIs in gic_common.h to a private header · e9ec3cec
      Soby Mathew authored
      This patch moves the private GIC common accessors from `gic_common.h` to
      a new private header file `gic_common_private.h`. This patch also adds
      additional comments to GIC register accessors to highlight the fact
      that some of them access register values that correspond to multiple
      interrupt IDs. The convention used is that the `set`, `get` and `clr`
      accessors access and modify the values corresponding to a single interrupt
      ID whereas the `read` and `write` GIC register accessors access the raw
      GIC registers and it could correspond to multiple interrupt IDs depending
      on the register accessed.
      
      Change-Id: I2643ecb2533f01e3d3219fcedfb5f80c120622f9
      e9ec3cec
    • Soby Mathew's avatar
      Fix GIC_IPRIORITYR setting in new drivers · 38a78614
      Soby Mathew authored
      The code to set the interrupt priority for secure interrupts in the
      new GICv2 and GICv3 drivers is incorrect. The setup code to configure
      interrupt priorities of secure interrupts, one interrupt at a time, used
      gicd_write_ipriorityr()/gicr_write_ipriority() function affecting
      4 interrupts at a time. This bug did not manifest itself because all the
      secure interrupts were configured to the highest secure priority(0) during
      cold boot and the adjacent non secure interrupt priority would be configured
      later by the normal world. This patch introduces new accessors,
      gicd_set_ipriorityr() and gicr_set_ipriorityr(), for configuring priority
      one interrupt at a time and fixes the the setup code to use the new
      accessors.
      
      Fixes ARM-software/tf-issues#344
      
      Change-Id: I470fd74d2b7fce7058b55d83f604be05a27e1341
      38a78614
    • Soby Mathew's avatar
      Fix race in GIC IPRIORITY and ITARGET accessors · a91e12fb
      Soby Mathew authored
      GICD_IPRIORITYR and GICD_ITARGETSR specifically support byte addressing
      so that individual interrupt priorities can be atomically updated by
      issuing a single byte write. The previous implementation of
      gicd_set_ipriority() and gicd_set_itargetsr() used 32-bit register
      accesses, modifying values for 4 interrupts at a time, using a
      read-modify-write approach. This potentially may cause concurrent changes
      by other CPUs to the adjacent interrupts to be corrupted. This patch fixes
      the issue by modifying these accessors to use byte addressing.
      
      Fixes ARM-software/tf-issues#343
      
      Change-Id: Iec28b5f5074045b00dfb8d5f5339b685f9425915
      a91e12fb
  2. 26 Nov, 2015 1 commit
    • Soby Mathew's avatar
      Add ARM GICv2 driver · 464ce2bb
      Soby Mathew authored
      This patch adds a driver for ARM GICv2 systems, example GIC-400. Unlike
      the existing GIC driver in `include/drivers/arm/arm_gic.h`, this driver
      is optimised for GICv2 and does not support GICv3 systems in GICv2
      compatibility mode. The driver interface has been implemented in
      `drivers/arm/gic/v2/gicv2_main.c`. The corresponding header is in
      `include/drivers/arm/gicv2.h`. Helper functions are implemented in
      `drivers/arm/gic/v2/gicv2_helpers.c` and are accessible through the
      `drivers/arm/gic/v2/gicv2_private.h` header.
      
      Change-Id: I09fffa4e621fb99ba3c01204839894816cd89a2a
      464ce2bb