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  1. 15 Nov, 2018 2 commits
  3. 09 Nov, 2018 2 commits
    • Yann Gautier's avatar
      stm32mp1: correct some static analysis tools issues · 3e6fab43
      Yann Gautier authored 
      

These issues wer found by sparse:

drivers/st/clk/stm32mp1_clk.c:1524:19:
 warning: incorrect type in assignment (different base types)
    expected restricted fdt32_t const [usertype] *pkcs_cell
    got unsigned int const [usertype] *

plat/st/stm32mp1/plat_image_load.c:13:6:
 warning: symbol 'plat_flush_next_bl_params' was not declared.
 Should it be static?
plat/st/stm32mp1/plat_image_load.c:21:16:
 warning: symbol 'plat_get_bl_image_load_info' was not declared.
 Should it be static?
plat/st/stm32mp1/plat_image_load.c:29:13:
 warning: symbol 'plat_get_next_bl_params' was not declared.
 Should it be static?

plat/st/stm32mp1/bl2_io_storage.c:40:10:
 warning: symbol 'block_buffer' was not declared. Should it be static?
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      3e6fab43
    • Siva Durga Prasad Paladugu's avatar
      arm64: versal: Add support for new Xilinx Versal ACAPs · f91c3cb1
      Siva Durga Prasad Paladugu authored 
      

Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar
Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with
leading-edge memory and interfacing technologies to deliver powerful
heterogeneous acceleration for any application. The Versal AI Core series has
five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm
Cortex-A72 application processors, dual-core Arm Cortex-R5 real-time
processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines
optimized for high-precision floating point with low latency.

This patch adds Virtual QEMU platform support for
this SoC "versal_virt".
Signed-off-by: default avatarSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
      f91c3cb1
  5. 08 Nov, 2018 4 commits
  7. 06 Nov, 2018 3 commits
  9. 05 Nov, 2018 1 commit
  11. 01 Nov, 2018 4 commits
  13. 31 Oct, 2018 2 commits
  15. 30 Oct, 2018 5 commits
  17. 29 Oct, 2018 5 commits
    • Antonio Nino Diaz's avatar
      plat/arm: Fix MISRA defects in SiP SVC handler · 15b94cc1
      Antonio Nino Diaz authored 
      

No functional changes.

Change-Id: I9b9f8d3dfde08d57706ad5450de6ff858a55ac01
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      15b94cc1
    • Deepak Pandey's avatar
      plat/arm: Introduce the N1SDP. · 80d37c28
      Deepak Pandey authored 
      

This patch adds support for the N1SDP (NeoVerse N1 System Development
Platform). It is an initial port and additional features are expected
to be added later.

The port includes only BL31 support as the System Control Processor
(SCP) is expected to take the role of primary boatloader

Change-Id: Ife17d8215a7bfcc1420204a72205e7ef920d0c10
Signed-off-by: default avatarDeepak Pandey <Deepak.Pandey@arm.com>
      80d37c28
    • Soby Mathew's avatar
      FVP: Enable PIE for RESET_TO_BL31=1 · fc922ca8
      Soby Mathew authored 
      

This patch enabled PIE for FVP when RESET_TO_BL31=1. The references
to BL31_BASE are replaced by BL31_START as being a symbol exported by
the linker, will create a dynamic relocation entry in .rela.dyn and
hence will be fixed up by dynamic linker at runtime. Also, we disable
RECLAIM_INIT_CODE when PIE is enabled as the init section overlay
creates some static relocations which cannot be handled by the
dynamic linker currently.

Change-Id: I86df1b0a8b2a8bbbe7c3f3c0b9a08c86c2963ec0
Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      fc922ca8
    • Soby Mathew's avatar
      plat/arm: Use `mov_imm` macro to load immediate values · bd83b396
      Soby Mathew authored 
      

This patch makes use of mov_imm macro where possible to load
immediate values within ARM platform layer.

Change-Id: I02bc7fbc1fa334c9fccf76fbddf515952f9a1298
Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      bd83b396
    • Soby Mathew's avatar
      Add helper to return reference to a symbol · 6a7b3005
      Soby Mathew authored 
      

This patch adds a utility function to return
the address of a symbol. By default, the compiler
generates adr/adrp instruction pair to return
the reference and this utility is used to override
this compiler generated to code and use `ldr`
instruction.

This is needed for Position Independent Executable
when it needs to reference a symbol which is constant
and does not depend on the execute address of the
binary.

For example, on the FVP, the GICv3 register context is
stored in a secure carveout (arm_el3_tzc_dram) within
DDR and does not relocate with the BL image. Now if
BL31 is executing at a different address other than
the compiled address, using adrp/adr instructions to
reference this memory will not work as they generate an
address that is PC relative. The way to get around this
problem is to reference it as non-PC relative (i.e
non-relocatable location) via `ldr` instruction.

Change-Id: I5008a951b007144258121690afb68dc8e12ee6f7
Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      6a7b3005
  19. 26 Oct, 2018 8 commits
  21. 25 Oct, 2018 4 commits
    • Antonio Nino Diaz's avatar
      Deprecate weak crash console functions · e74afb65
      Antonio Nino Diaz authored 
      

The default behaviour of the plat_crash_console_xxx functions isn't
obvious to someone that hasn't read all the documentation. As they are
not mandatory, it is unlikely that the code will be checked when doing a
platform port, which may mean that some platforms may not have crash
console support at all.

The idea of this patch is to force platform maintainers to decide how
the crash console has to behave so that the final behaviour isn't
unexpected.

Change-Id: I40b2a7b56c5530c1dcd63eace5bd37ae6335056e
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      e74afb65
    • Antonio Nino Diaz's avatar
      rockchip: Use common crash console functions · a9d5a3ff
      Antonio Nino Diaz authored 
      

This platform depends on weak functions defined in
``plat/common/aarch64/platform_helpers.S`` that are going to be removed.

Change-Id: I5104d091c32271d77ed9690e9dc257c061289def
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      a9d5a3ff
    • Antonio Nino Diaz's avatar
      Add sample crash console functions · 6c9ada31
      Antonio Nino Diaz authored 
      

Platforms that wish to use the sample functions have to add the file to
their Makefile. It is not included by default.

Change-Id: I713617bb58dc218967199248f68da86241d7ec40
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      6c9ada31
    • Antonio Nino Diaz's avatar
      plat/arm: Make crash console functions strong · c02c69f8
      Antonio Nino Diaz authored 
      

In Arm platforms the crash console doesn't print anything if the crash
happens early enough. This happens in all images, not only BL1. The
reason is that they the files ``plat/common/aarch64/platform_helpers.S``
and ``plat/arm/common/aarch64/arm_helpers.S``, and the crash console
functions are defined as weak in both files. In practice, the linker
can pick the one in ``plat/common``, which simply switches the multi
console to crash mode when it wants to initialize the crash console.
In the case of Arm platforms, there are no console drivers registered
at that point, so nothing is printed.

This patch makes the functions in plat/arm strong so that they override
the weak functions in plat/common.

Change-Id: Id358db7d2567d7df0951790a695636cf6c9ac57f
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      c02c69f8