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  1. 05 Jan, 2021 1 commit
    • Marek Behún's avatar
      plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor · d9243f26
      Marek Behún authored 
      

Introduce a new build option CM3_SYSTEM_RESET for A3700 platform, which,
when enabled, adds code to the PSCI reset handler to try to do system
reset by the WTMI firmware running on the Cortex-M3 secure coprocessor.
(This function is exposed via the mailbox interface.)

The reason is that the Turris MOX board has a HW bug which causes reset
to hang unpredictably. This issue can be solved by putting the board in
a specific state before reset.
Signed-off-by: default avatarMarek Behún <marek.behun@nic.cz>
Change-Id: I3f60b9f244f334adcd33d6db6a361fbc8b8d209f
      d9243f26
  3. 19 Nov, 2020 1 commit
  5. 13 Oct, 2020 1 commit
  7. 11 Oct, 2020 1 commit
  9. 04 Oct, 2020 1 commit
  11. 02 Oct, 2020 3 commits
  13. 29 Sep, 2020 1 commit
  15. 28 Sep, 2020 1 commit
  17. 18 Aug, 2020 1 commit
  19. 17 Aug, 2020 1 commit
  21. 10 Aug, 2020 1 commit
  23. 03 Aug, 2020 1 commit
  25. 31 Jul, 2020 1 commit
  27. 30 Jul, 2020 4 commits
  29. 22 Jul, 2020 1 commit
  31. 21 Jul, 2020 1 commit
  33. 10 Jul, 2020 2 commits
    • Konstantin Porotchkin's avatar
      plat: marvell: armada: a8k: change CCU LLC SRAM mapping · 0a977b9b
      Konstantin Porotchkin authored 
      

The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage.
The CCU have to prepare SRAM window, but point to the DRAM-0 target
until the SRAM is actually enabled.
This patch changes CCU SRAM window target to DRAM-0
Remove dependence between LLC_SRAM and LLC_ENABLE and update the
build documentation.
The SRAМ base moved to follow the OP-TEE SHMEM area (0x05400000)

Change-Id: I85c2434a3d515ec37da5ae8eb729e3280f91c456
Signed-off-by: default avatarKonstantin Porotchkin <kostap@marvell.com>
      0a977b9b
    • Jacky Bai's avatar
      plat: imx8mp: Add the basic support for i.MX8MP · a775ef25
      Jacky Bai authored 
      

The i.MX 8MP Media Applications Processor is part of the growing
i.MX8M family targeting the consumer and industrial market. It brings
an effective Machine Learning and AI accelerator that enables a new
class of applications. It is built in 14LPP to achieve both high
performance and low power consumption and relies on a powerful fully
coherent core complex based on a quad core Arm Cortex-A53 cluster and
Cortex-M7 low-power coprocessor, audio digital signal processor, machine
learning and graphics accelerators.
Signed-off-by: default avatarJacky Bai <ping.bai@nxp.com>
Change-Id: I98311ebc32bee20af05031492e9fc24d06e55f4a
      a775ef25
  35. 04 Jul, 2020 3 commits
  37. 01 Jul, 2020 1 commit
  39. 19 Jun, 2020 1 commit
  41. 09 Jun, 2020 1 commit
    • Andre Przywara's avatar
      GICv3: GIC-600: Detect GIC-600 at runtime · b4ad365a
      Andre Przywara authored 
      

The only difference between GIC-500 and GIC-600 relevant to TF-A is the
differing power management sequence.
A certain GIC implementation is detectable at runtime, for instance by
checking the IIDR register. Let's add that test before initiating the
GIC-600 specific sequence, so the code can be used on both GIC-600 and
GIC-500 chips alike, without deciding on a GIC chip at compile time.

This means that the GIC-500 "driver" is now redundant. To allow minimal
platform support, add a switch to disable GIC-600 support.

Change-Id: I17ea97d9fb05874772ebaa13e6678b4ba3415557
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      b4ad365a
  43. 06 Jun, 2020 2 commits
  45. 27 May, 2020 1 commit
    • Usama Arif's avatar
      plat/arm: Introduce TC0 platform · f5c58af6
      Usama Arif authored 
      

This patch adds support for Total Compute (TC0) platform. It is an
initial port and additional features are expected to be added later.

TC0 has a SCP which brings the primary Cortex-A out of reset
which starts executing BL1. TF-A optionally authenticates the SCP
ram-fw available in FIP and makes it available for SCP to copy.

Some of the major features included and tested in this platform
port include TBBR, PSCI, MHUv2 and DVFS.

Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef
Signed-off-by: default avatarUsama Arif <usama.arif@arm.com>
      f5c58af6
  47. 22 May, 2020 1 commit
  49. 15 Apr, 2020 2 commits
  51. 03 Apr, 2020 1 commit
  53. 31 Mar, 2020 1 commit
  55. 14 Mar, 2020 1 commit
  57. 09 Mar, 2020 1 commit
  59. 27 Feb, 2020 1 commit