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  1. 31 Jan, 2019 24 commits
  3. 23 Jan, 2019 16 commits
    • Varun Wadekar's avatar
      Tegra186: remove RELOCATE_TO_BL31_BASE config · 8ec45621
      Varun Wadekar authored 
      

This patch removes this unused config option from the Tegra186
platform makefiles.

Change-Id: Idcdf6854332a26599323a247289c2d3ce19f475f
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      8ec45621
    • Varun Wadekar's avatar
      Tegra: memctrl_v2: remove usage of ENABLE_SMMU_DEVICE config · fc5adf7d
      Varun Wadekar authored 
      

This patch removes the usage of this platform config, as it is always
enabled by all the supported platforms.

Change-Id: Ie7adb641adeb3604b177b6960b797722d60addfa
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      fc5adf7d
    • Dilan Lee's avatar
      Tegra: add 'late' platform setup handler · 3e1923d9
      Dilan Lee authored 
      

This patch adds a platform setup handler that gets called after
the MMU is enabled. Platforms wanting to make use of this handler
should declare 'plat_late_platform_setup' handler in their platform
files, to override the default weakly defined handler.

Change-Id: Ibc97a2e5a24608ddea856d0bd543a9d5876f604c
Signed-off-by: default avatarDilan Lee <dilee@nvidia.com>
      3e1923d9
    • Varun Wadekar's avatar
      Tegra: spe: shared console for Tegra platforms · dd20f5b3
      Varun Wadekar authored 
      

There are Tegra platforms which have limited UART ports and so
all the components have to share the console. The SPE helps out
by collecting all the logs in such cases and prints them on the
shared UART port.

This patch adds a driver to communicate with the SPE driver, which
in turn provides the console.

Change-Id: Ie750520b936b8bed0ab1d876f03fc0a3490a85a3
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      dd20f5b3
    • Varun Wadekar's avatar
      Tegra: console driver compilation from platform makefiles · 4cba6985
      Varun Wadekar authored 
      

This patch includes the console driver from individual platform
makefiles and removes it from tegra_common.mk. This allows future
platforms to include consoles of their choice.

Change-Id: I7506562bfac78421a80fb6782ac8472fbef6cfb0
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      4cba6985
    • Varun Wadekar's avatar
      Tegra: smmu: change exit criteria for context size calculation · 2ad1bddc
      Varun Wadekar authored 
      

Tegra SoCs currently do not have a SMMU register at address 0xFFFFFFFF.
This patch changes the search criteria, to look for this marker, to
calculate the size of the saved context.

Change-Id: I15d91945ecb78267f91c45f37985dbb2327ca3ae
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      2ad1bddc
    • Steven Kao's avatar
      Tegra: memctrl_v2: platform handler for TZDRAM setup · c63ec263
      Steven Kao authored 
      

The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers to perform custom steps during TZDRAM setup.

Change-Id: Iee094d6ca189c6dd24f1147003c33c99ff3a953b
Signed-off-by: default avatarSteven Kao <skao@nvidia.com>
      c63ec263
    • Varun Wadekar's avatar
      Tegra186: save system suspend entry marker to TZDRAM · 539c62d7
      Varun Wadekar authored 
      

This patch adds support to save the system suspend entry and exit
markers to TZDRAM to help the trampoline code decide if the current
warmboot is actually an exit from System Suspend.

The Tegra186 platform handler sets the system suspend entry marker
before entering SC7 state and the trampoline flips the state back to
system resume, on exiting SC7.

Change-Id: I29d73f1693c89ebc8d19d7abb1df1e460eb5558e
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      539c62d7
    • Varun Wadekar's avatar
      Tegra186: helper functions for CPU rst handler and SMMU ctx offset · 889c07c7
      Varun Wadekar authored 
      

This patch adds a helper function to get the SMMU context's offset
and uses another helper function to get the CPU trampoline offset.
These helper functions are used by the System Suspend entry sequence
to save the SMMU context and CPU reset handler to TZDRAM.

Change-Id: I95e2862fe37ccad00fa48ec165c6e4024df01147
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      889c07c7
    • Varun Wadekar's avatar
      Tegra: bpmp: return error if BPMP init fails · d7be5e2e
      Varun Wadekar authored 
      

This patch returns error if BPMP initialization fails. The platform
code marks the cluster as "runnning" since we wont be able to get
it into the low power state without BPMP.

Change-Id: I86f51d478626240bb7b4ccede8907674290c5dc1
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      d7be5e2e
    • Steven Kao's avatar
      Tegra: rename secure scratch register macros · 601a8e54
      Steven Kao authored 
      

This patch renames all the secure scratch registers to reflect their
usage.

This is a list of all the macros being renamed:

- SECURE_SCRATCH_RSV1_* -> SCRATCH_RESET_VECTOR_*
- SECURE_SCRATCH_RSV6 -> SCRATCH_SECURE_BOOTP_FCFG
- SECURE_SCRATCH_RSV11_* -> SCRATCH_SMMU_TABLE_ADDR_*
- SECURE_SCRATCH_RSV53_* -> SCRATCH_BOOT_PARAMS_ADDR_*
- SECURE_SCRATCH_RSV55_* -> SCRATCH_TZDRAM_ADDR_*

NOTE: Future SoCs will have to define these macros to
      keep the drivers functioning.

Change-Id: Ib3ba40dd32e77b92b47825f19c420e6fdfa8b987
Signed-off-by: default avatarSteven Kao <skao@nvidia.com>
      601a8e54
    • Varun Wadekar's avatar
      Tegra: memctrl_v2: platform handler for TZDRAM settings · d5bd0de6
      Varun Wadekar authored 
      

The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers to perform platform specific steps, e.g. enable encryption,
save base/size to secure scratch registers.

Change-Id: Ifaa2e0eac20b50f77ec734256544c36dd511bd63
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      d5bd0de6
    • Varun Wadekar's avatar
      Tegra186: secondary: fix MISRA violations for Rules 8.6, 11.1 · 7191566c
      Varun Wadekar authored 
      

This patch fixes the following MISRA violations:

Rule 8.6: Externally-linked object or function has "no" definition(s).
Rule 11.1: A cast shall not convert a pointer to a function to
any other type.

Change-Id: Ic1f6fc14c744e54ff782c6987dab9c9430410f5e
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      7191566c
    • Varun Wadekar's avatar
      Tegra186: sanity check target cluster during core power on · b6d1757b
      Varun Wadekar authored 
      

This patch sanity checks the target cluster value, during core power on,
by comparing it against the maximum number of clusters supported by the
platform.

Reported by: Rohit Khanna <rokhanna@nvidia.com>

Change-Id: Ia73ccf04bd246403de4ffff6e5c99e3b00fb98ca
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      b6d1757b
    • Anthony Zhou's avatar
      Tegra186: setup: Fix MISRA Rule 8.4 violation · ad67f8c5
      Anthony Zhou authored 
      

MISRA Rule 8.4, A compatible declaration shall be visible when an
object or function with external linkage is defined.

This patch adds static for local array to fix this defect.

Change-Id: I8231448bf1bc0b1e59611d7645ca983b83d5c8e3
Signed-off-by: default avatarAnthony Zhou <anzhou@nvidia.com>
      ad67f8c5
    • Varun Wadekar's avatar
      Tegra: bpmp_ipc: IPC driver to communicate with BPMP firmware · 26e2b93a
      Varun Wadekar authored 
      

This patch adds the driver to communicate with the BPMP firmware on Tegra
SoCs, starting Tegra186. BPMP firmware is responsible for clock enable/
disable requests, module resets among other things.

MRQ is short for Message ReQuest. This is the general purpose, multi channel
messaging protocol that is widely used to communicate with BPMP. This is further
divided into a common high level protocol and a peer-specific low level protocol.
The higher level protocol specifies the peer identification, channel definition
and allocation, message structure, message semantics and message dispatch process
whereas the lower level protocol defines actual message transfer implementation
details. Currently, BPMP supports two lower level protocols - Token Mail Operations
(TMO), IVC Mail Operations (IMO).

This driver implements the IMO protocol. IMO is implemented using the IVC (Inter-VM
Communication) protocol which is a lockless, shared memory messaging queue management
protocol.

The IVC peer is expected to perform the following as part of establishing a connection
with BPMP.

1. Initialize the channels with tegra_ivc_init() or its equivalent.
2. Reset the channel with tegra_ivc_channel_reset. The peer should also ensure that
   BPMP is notified via the doorbell.
3. Poll until the channel connection is established [tegra_ivc_channel_notified() return
   0]. Interrupt BPMP with doorbell each time after tegra_ivc_channel_notified() return
   non zero.

The IPC driver currently supports reseting the GPCDMAand XUSB_PADCTL hardware blocks. In
future, more hardware blocks would be supported.

Change-Id: I52a4bd3a853de6c4fa410904b6614ff1c63df364
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      26e2b93a