- 23 Jan, 2020 3 commits
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laurenw-arm authored
Setting errata workarounds for N1 1043202 and 1315703 to 0 since they should be turned off by default. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I116673a4ddcf64436e90d70133f035a133989ed9
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Manish Pandey authored
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Manish Pandey authored
Out of two possible implementation of Secure Partition Manager(SPM) currently only Management mode (MM) design is supported and the support for SPM based on SPCI Alpha 1 prototype has been removed. Earlier both implementation used common build flag "ENABLE_SPM" but it has since been decoupled and MM uses a separate build FLAG "SPM_MM". Instructions to build it for FVP was still using "ENABLE_SPM", which has beend corrected in this patch. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I505b98173d6051816436aa602ced6dbec4efc776
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- 22 Jan, 2020 8 commits
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Mark Dykes authored
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Mark Dykes authored
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Sandrine Bailleux authored
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Soby Mathew authored
* changes: plat: xilinx: Move pm_client.h to common directory plat: xilinx: versal: Make silicon default build target xilinx: versal: Wire silicon default setup versal: Increase OCM memory size for DEBUG builds plat: xilinx: versal: Dont set IOU switch clock arm64: versal: Adjust cpu clock for versal virtual xilinx: versal: Add support for PM_GET_OPERATING_CHARACTERISTIC EEMI call plat: versal: Add Get_ChipID API plat: xilinx: versal: Add load Pdi API support xilinx: versal: Add feature check API xilinx: versal: Implement set wakeup source for client plat: xilinx: versal: Add GET_CALLBACK_DATA function xilinx: versal: Add PSCI APIs for system shutdown & reset xilinx: versal: Add PSCI APIs for suspend/resume xilinx: versal: Remove no_pmc ops to ON power domain xilinx: versal: Add set wakeup source API xilinx: versal: Add client wakeup API xilinx: versal: Add query data API xilinx: versal: Add request wakeup API xilinx: versal: Add PM_INIT_FINALIZE API for versal xilinx: versal: Add support of PM_GET_TRUSTZONE_VERSION API xilinx: versal: enable ipi mailbox service xilinx: move ipi mailbox svc to xilinx common plat: xilinx: versal: Implement PM IOCTL API xilinx: versal: Implement power down/restart related EEMI API xilinx: versal: Add SMC handler for EEMI API xilinx: versal: Implement PLL related PM APIs xilinx: versal: Implement clock related PM APIs xilinx: versal: Implement pin control related PM APIs xilinx: versal: Implement reset related PM APIs xilinx: versal: Implement device related PM APIs xilinx: versal: Add support for suspend related APIs xilinx: versal: Add get_api_version support xilinx: Add support to send PM API to PMC using IPI for versal plat: xilinx: versal: Move versal_def.h to include directory plat: xilinx: versal: Move versal_private.h to include directory plat: xilinx: zynqmp: Use GIC framework for warm restart
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Sandrine Bailleux authored
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Andre Przywara authored
Moving the FDT helper functions to the common/ directory exposed the file to MISRA checking, which is mandatory for common code. Fix the complaints that the test suite reported. Change-Id: Ica8c8a95218bba5a3fd92a55407de24df58e8476 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Madhukar Pappireddy authored
In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence mandate the build to require that ARM_BL31_IN_DRAM is enabled as well. Naturally with SEPARATE_NOBITS_REGION enabled, the BL31 initialization code cannot be reclaimed to be used for runtime data such as secondary cpu stacks. Memory map for BL31 NOBITS region also has to be created. Change-Id: Ibd480f82c1dc74e9cbb54eec07d7a8fecbf25433 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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Madhukar Pappireddy authored
Since BL31 PROGBITS and BL31 NOBITS sections are going to be in non-adjacent memory regions, potentially far from each other, some fixes are needed to support it completely. 1. adr instruction only allows computing the effective address of a location only within 1MB range of the PC. However, adrp instruction together with an add permits position independent address of any location with 4GB range of PC. 2. Since BL31 _RW_END_ marks the end of BL31 image, care must be taken that it is aligned to page size since we map this memory region in BL31 using xlat_v2 lib utils which mandate alignment of image size to page granularity. Change-Id: Ic745c5a130fe4239fa2742142d083b2bdc4e8b85 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 21 Jan, 2020 5 commits
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Manish Pandey authored
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Olivier Deprez authored
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Manish Pandey authored
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Sandrine Bailleux authored
* changes: plat: imx: Correct the SGIs that used for secure interrupt plat: imx8mm: Add the support for opteed spd on imx8mq/imx8mm
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Sandrine Bailleux authored
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- 20 Jan, 2020 24 commits
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Manish Pandey authored
* changes: Tegra194: platform handler for entering CPU standby state Tegra194: memctrl: force viw and vifalr/w transactions as non-coherent Tegra194: memctrl: fix bug in client order id reg value generation Tegra194: memctrl: enable mc coalescer Tegra194: update scratch registers used to read boot parameters Tegra194: implement system shutdown/reset handlers Tegra194: mce: support for shutdown and reboot Tegra194: request CG7 before checking if SC7 is allowed Tegra194: config to enable/disable strict checking mode Tegra194: remove unused platform configs Tegra194: restore XUSB stream IDs on System Resume
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Samuel Holland authored
Remove the general BL31 mmap region: it duplicates the existing static mapping for the entire SRAM region. Use the helper definitions when applicable to simplify the code and add the MT_EXECUTE_NEVER flag. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I7a6b79e50e4b5c698774229530dd3d2a89e94a6d
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Manish Pandey authored
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Manish Pandey authored
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Manish Pandey authored
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Soby Mathew authored
* changes: doc: stm32mp1: Update build command line fdts: stm32mp1: remove second QSPI flash instance stm32mp1: Add support for SPI-NOR boot device stm32mp1: Add support for SPI-NAND boot device spi: stm32_qspi: Add QSPI support fdts: stm32mp1: update for FMC2 pin muxing stm32mp1: Add support for raw NAND boot device fmc: stm32_fmc2_nand: Add FMC2 driver support stm32mp1: Reduce MAX_XLAT_TABLES to 4 io: stm32image: fix device_size type stm32mp: add DT helper for reg by name stm32mp1: add compilation flags for boot devices lib: utils_def: add CLAMP macro compiler_rt: Import popcountdi2.c and popcountsi2.c files Add SPI-NOR framework Add SPI-NAND framework Add SPI-MEM framework Add raw NAND framework
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Lionel Debieve authored
Add new flags for storage support that must be used in the build command line. Add the complete build steps for an OP-TEE configuration. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I0c682f6eb0aab83aa929f4ba734d3151c264aeed
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Lionel Debieve authored
Remove second flash node as only one must be used by QSPI NOR driver. Change-Id: I48189f2fdf4e0455aabe7d4cd9b2f3d36bb9cfb5 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Lionel Debieve authored
STM32MP1 platform is able to boot from SPI-NOR devices. These modifications add this support using the new SPI-NOR framework. Change-Id: I75ff9eba4661f9fb87ce24ced2bacbf8558ebe44 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Lionel Debieve authored
STM32MP1 platform is able to boot from SPI-NAND devices. These modifications add this support using the new SPI-NAND framework. Change-Id: I0d5448bdc4bde153c1209e8043846c0f935ae5ba Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Lionel Debieve authored
Add QSPI support (limited to read interface). Implements the memory map and indirect modes. Low level driver based on SPI-MEM operations. Change-Id: Ied698e6de3c17d977f8b497c81f2e4a0a27c0961 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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Lionel Debieve authored
Include the required FMC2 pinmux definition for the NAND management. Change-Id: I80333deacdf3444b2f21f17f2fb5919e569a3591 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Lionel Debieve authored
STM32MP1 platform is able to boot from raw NAND devices. These modifications add this support using the new raw NAND framework. Change-Id: I9e9c2b03930f98a5ac23f2b6b41945bef43e5043 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Lionel Debieve authored
Add fmc2_nand driver support. The driver implements only read interface for NAND devices. Change-Id: I3cd037e8ff645ce0d217092b96f33ef41cb7a522 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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Nicolas Le Bayon authored
For STM32MP1, the address space is 4GB, which can be first divided in 4 parts of 1GB. This LVL1 table is already mapped regardless of MAX_XLAT_TABLES. Fixing typo: Replace Ko to KB. BL2/sp_min for platform STM32MP1 requires 4 MMU translation tables: - a level2 table and a level3 table for identity mapped SYSRAM - a level2 table mapping 2MB of BootROM runtime resources - a level2 table mapping 2MB of secure DDR (case BL32 is OP-TEE) Change-Id: If80cbd4fccc7689b39dd540d6649b1313557f326 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Lionel Debieve authored
Device size could be more than 4GB, we must define size as unsigned long long. Change-Id: I52055cf5c1c15ff18ab9e157aa9b73c8b4fb7b63 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Lionel Debieve authored
Add a new entry to find register properties by name and include new assert functions to limit address cells to 1 and size cells to 1. Change-Id: Ide59a795a05fb2af36bd07fec15e5a3adf196226 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Nicolas Le Bayon authored
Adds compilation flags to specify which drivers will be embedded in the generated firmware. Change-Id: Ie9decc89c3f26cf17e7148a3a4cf337fd35940f7 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Lionel Debieve authored
Add the standard CLAMP macro. It ensures that x is between the limits set by low and high. If low is greater than high the result is undefined. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: Ia173bb9ca51bc8d9a8ec573bbc15636a94f881f4
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Lionel Debieve authored
Imported from the LLVM compiler_rt library on master branch as of 30 Oct 2018 (SVN revision: r345645). This is to get the __popcountsi2(si_int a) and __popcountdi2(di_int a) builtin which are required by a driver that uses a __builtin_popcount(). Change-Id: I8e0d97cebdd90d224690c8ce1b02e657acdddb25 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Lionel Debieve authored
SPI-NOR framework is based on SPI-MEM framework using spi_mem_op execution interface. It implements read functions and allows NOR configuration up to quad mode. Default management is 1 data line but it can be overridden by platform. It also includes specific quad mode configuration for Spansion, Micron and Macronix memories. Change-Id: If49502b899b4a75f6ebc3190f6bde1013651197f Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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Lionel Debieve authored
This framework supports SPI-NAND and is based on the SPI-MEM framework for SPI operations. It uses a common high level access using the io_mtd. It is limited to the read functionalities. Default behavior is the basic one data line operation but it could be overridden by platform. Change-Id: Icb4e0887c4003a826f47c876479dd004a323a32b Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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Lionel Debieve authored
This framework supports SPI operations using a common spi_mem_op structure: - command - addr - dummy - data The framework manages SPI bus configuration: - speed - bus width (Up to quad mode) - chip select Change-Id: Idc2736c59bfc5ac6e55429eba5d385275ea3fbde Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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Lionel Debieve authored
The raw NAND framework supports SLC NAND devices. It introduces a new high level interface (io_mtd) that defines operations a driver can register to the NAND framework. This interface will fill in the io_mtd device specification: - device_size - erase_size that could be used by the io_storage interface. NAND core source file integrates the standard read loop that performs NAND device read operations using a skip bad block strategy. A platform buffer must be defined in case of unaligned data. This buffer must fit to the maximum device page size defined by PLATFORM_MTD_MAX_PAGE_SIZE. The raw_nand.c source file embeds the specific NAND operations to read data. The read command is a raw page read without any ECC correction. This can be overridden by a low level driver. No generic support for write or erase command or software ECC correction. NAND ONFI detection is available and can be enabled using NAND_ONFI_DETECT=1. For non-ONFI NAND management, platform can define required information. Change-Id: Id80e9864456cf47f02b74938cf25d99261da8e82 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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