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  1. 04 Sep, 2018 8 commits
    • Bryan O'Donoghue's avatar
      imx: imx_clock: uart: Add UART clock API · dcd54e9b
      Bryan O'Donoghue authored 
      

This patch adds an API to configure up the base UART clocks, taking a
bit-mask of silicon specific bits as an input from a higher layer in order
to direct the necessary clock source.
Signed-off-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
      dcd54e9b
    • Bryan O'Donoghue's avatar
      imx: imx_clock: Add driver and associated clock register definitions · 82e35083
      Bryan O'Donoghue authored 
      

This commit:

- Defines a clock stub with a conjoined header defining the clock
  memory map.

- Defines the CCM Clock Gating Register which comes in a quadrumvirate
  register set to read, set, clear and toggle individual clock gates into
  one of four states based bitmask.

  00: Domain clocks not needed
  01: Domain clocks needed when in RUN
  10: Domain clocks needed when in RUN and WAIT
  11: Domain clocks needed all the time

- Defines clock control register bits

  There are various quadrumvirate register blocks target-root, misc-root,
  post-root, pre-root in the CCM.

  The number of registers is huge but the four registers in each
  quadrumvirate block contain the same bits, so the number of bit
  definitions is actually quite low.

- Defines clock identifiers

  An array of clock gates is provided in the CCM block. In order to index
  that array and thus enable/disable clock gates for the right components,
  we need to provide meaningful names to the indices.

  Section 5.2.5 of the i.MX7 Solo Application Processor Reference Manual
  Rev 0.1 provides the relevant details.

- Defines target mux select bits
  This is a comprehensive definition of the target clock mux select bits.
  These bits are required to correctly select the clock source. Defining
  all of the bits up-front even for unused blocks in ATF means we can
  switch on any block we want at a later date without having to write new
  code in the clock-mux layer.

- Defines identifier indices into root-slice array
  The root-slice array of control registers has a specific set of indices,
  which differ from the clock-gate indices.

- Provides a clock gate enable/disable routine
  Provides a clock-gate enable/disable routine via the set/clr
  registers in a given clock-gate control register block.

  This index passed should be one of the enums associated with CCM and
  depending on enable/disable being passed either set or clr will be
  written to.

  The Domain0 bits are currently the only bits targeted by this write, more
  work may need to be done on the domain bits in subsequent patches as a
  result.

- imx: Adds set/clr routines to clock layer

  Adds a set and clr routine to the clock layer. These routines allow us to
  access the set and clear registers of the "target" block registers. These
  are the registers where we select the clock source from the available list.
Signed-off-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
      82e35083
    • Bryan O'Donoghue's avatar
      imx7: imx_regs: Add a shared imx-regs.h for i.MX7 ATF platforms · 7d464592
      Bryan O'Donoghue authored 
      

In order to have some common code shared between similar SOCs its pretty
common to have IP blocks reused. In reusing those blocks we frequently need
to map compatible blocks to different addresses depending on the SOC.

This patch adds a basic memory map of the i.MX7 based on the "Cortex-A7
Memory Map" section 2.12 of "i.MX7Solo Applications Processor Reference
Manual, Rev 0.1 08/2016"

In memory map terms the i.MX7S and i.MX7D are identical with the D
variant containing two Cortex-A7 cores plus a Cortex-M core and the S
variant containing one Cortex-A7 and one Cortex-M.
Signed-off-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
      7d464592
    • Jun Nie's avatar
      drivers: imx: mxc_usdhc: Add USDHC driver to support boot EMMC · 8b659130
      Jun Nie authored 
      

Add USDHC driver to support boot EMMC. Only initialization
and single/multiple block read are tested.

[bod: fixed checkpatch.pl complaints]
[bod: changed name to imx_usdhc for namespace consistency]
[bod: squashed antecedent fixes into this one patch]
Signed-off-by: default avatarJun Nie <jun.nie@linaro.org>
Signed-off-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
      8b659130
    • Bryan O'Donoghue's avatar
      drivers: mmc: Add missing response type for some commands · 61752898
      Bryan O'Donoghue authored 
      

Add missing response type for SWITCH command and STOP_TRANSMISSION
so that controller can be configured accordingly.

[bod: ported this change from Jun's eMMC patches to the MMC driver]
Signed-off-by: default avatarJun Nie <jun.nie@linaro.org>
Signed-off-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
      61752898
    • Bryan O'Donoghue's avatar
      drivers: mmc: Fix R3 response type definition · 94522ff7
      Bryan O'Donoghue authored 
      

The R3 response type definition should be (1 << 0). Make sure we define the
expected response code in the appropriate fashion.
Signed-off-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
      94522ff7
    • Jun Nie's avatar
      drivers: emmc: dw_mmc: Add response flag into response ID definition · 2a82a9c9
      Jun Nie authored 
      

Add response flag into ID definition so that driver does not
need to handle it again.
Signed-off-by: default avatarJun Nie <jun.nie@linaro.org>
Signed-off-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
      2a82a9c9
    • Jun Nie's avatar
      drivers: imx: imx_gpt: Add general purpose timer API binding · e67606cf
      Jun Nie authored 
      

Add delay timer API so that it can be called by delay timer
layer and used as delay timer globally.

[bod: changed name from imx_delay_timer -> imx_gpt ]
Signed-off-by: default avatarJun Nie <jun.nie@linaro.org>
Reviewed-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
      e67606cf
  3. 30 Aug, 2018 25 commits
  5. 29 Aug, 2018 1 commit
  7. 28 Aug, 2018 5 commits
  9. 23 Aug, 2018 1 commit