- 08 Dec, 2020 2 commits
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Ravi Patel authored
Current implementation doesn't support change of div1 value if clk has 2 divisor because div1 clk is the parent of the div2 clk and div2 clk does not have SET_RATE_PARENT flag. This causes div1 value to be fixed and only value of div2 will be adjusted according to required clock rate. Example: Consider a case of nand_ref clock which has 2 divisor and 1 mux. The frequency of mux clock is 1500MHz and default value of div1 and div2 is 15 and 1 respectively. So the final clock will be of 100MHz. When driver requests 80MHz for nand_ref clock, clock framework will adjust the div2 value to 1 (setting div2 value 2 results final clock to 50MHz which is more inaccurate compare to 100Mhz) which results final clock to 100MHz. Ideally the value of div1 and div2 should be updated to 19 and 1 respectively so that final clock goes to around 78MHz. This patch fixes above problem by allowing change in div1 value. Signed-off-by:
Ravi Patel <ravi.patel@xilinx.com> Signed-off-by:
Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: Ibb98f6748d28653fdd1e59bf433b6a37ce9c1a58
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Siva Durga Prasad Paladugu authored
This patches copies only the valid part of string and avoids filling junk at the end. Signed-off-by:
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by:
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- 07 Dec, 2020 1 commit
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Tejas Patel authored
For boot health status PMU Global General Storage Register 4 is used. GGS4 can be used for other purpose along with boot health status. So, change its name from PM_BOOT_HEALTH_STATUS_REG to PMU_GLOBAL_GEN_STORAGE4. Signed-off-by:
Tejas Patel <tejas.patel@xilinx.com> Signed-off-by:
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- 12 Nov, 2020 2 commits
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Davorin Mista authored
All EEMI error codes start with value 2000. Note: Legacy error codes ARGS (=1) and NOTSUPPORTED (=4) returned by current ATF code have been left in place. Signed-off-by:
Davorin Mista <davorin.mista@aggios.com> Acked-by:
Will Wong <WILLW@xilinx.com> Signed-off-by:
Michal Simek <michal.simek@xilinx.com> Change-Id: I939afa85957cac88025d82a80f9f6dd49be993b6
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Mirela Simonovic authored
Linux clock framework cannot properly deal with these errors. When the error is related to the lack of permissions to control the clock we filter the error and report the success to linux. Before recent changes in clock framework across the stack, this was done in the PMU-FW as a workaround. Since the PMU-FW now handles clocks and the permissions to control them using general principles rather than workarounds, it can no longer distinguish such exceptions and it has to return no-access error. Signed-off-by:
Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by:
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- 30 Jan, 2020 1 commit
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Tejas Patel authored
To find result count use ARRAY_SIZE for better readability. Signed-off-by:
Jolly Shah <jolly.shah@xilinx.com> Change-Id: I97201de4d43024e59fa78bd61937c86d47724ab5
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- 22 Jan, 2020 1 commit
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Norbert Werner authored
Signed-off-by:Norbert Werner <opensource@lab-w.org> Change-Id: I3264515e5901689328861964ff664ff08b6e852c
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- 15 Jan, 2020 7 commits
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Tejas Patel authored
Move pm_client.h to common directory to avoid duplication of function declaration. Signed-off-by:
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Siva Durga Prasad Paladugu authored
- Flag GICV2_G0_FOR_EL3 needs to be set for group interrupts to be targeted to EL3. - Raise SGI interrupts for individual CPU cores as GIC API uses CPU num as parameter, not CPU mask. - Flag WARMBOOT_ENABLE_DCACHE_EARLY needs to be set to enable CPU interface mask work properly for all CPU cores which is required when generating SGI. - Call plat_ic_end_of_interrupt() from ttc_fiq_handler() to clear GIC interrupt to avoid same interrupt again. Signed-off-by:
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Rajan Vaja authored
Add new QID to get maximum supported divisor by clock. Signed-off-by:
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Ravi Patel authored
Existing implementation does not allow to change the value of the DIV1 because DIV2 does not have SET_RATE_PARENT flag. This causes DIV1 value to be fixed and only value of DIV2 will be adjusted according to required clock rate. Signed-off-by:
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Rajan Vaja authored
Linux expects custom flags in type flags. So move custom flags to type flags instead of providing them to clock core flags. Signed-off-by:
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Rajan Vaja authored
Add support to add extra custom type flags and provide to caller in topology query. Signed-off-by:
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Rajan Vaja authored
Add GET_CALLBACK_DATA function again as now Linux driver supports both mailbox as well as ISR method. Signed-off-by:
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- 07 Jan, 2020 4 commits
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Rajan Vaja authored
CLK_TOPSW_LSBUS is parent of WDT clock. Clock from invalid clock list would not be registered to CCF framework and so cannot be used as parent of other clocks. WDT clock has default parent as CLK_TOPSW_LSBUS(APB clock). If CLK_TOPSW_LSBUS is not registered, CCF would not recognize that clock and hence rate of WDT clock would be calculated to be 0 by CCF(as parent rate is considered 0). So it is necessary to allow registration of CLK_TOPSW_LSBUS clock. Signed-off-by:
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Mounika Grace Akula authored
This patch adds LPD WDT clock node to the pm_clock clocks structure list so that LPD WDT can be used from Linux. Also this patch removes the CLK_LPD_LSBUS from invalid clock list to allow the registration of this clock to CCF framework as it is the parent of LPD WDT. Signed-off-by:
Mounika Grace Akula <mounika.grace.akula@xilinx.com> Signed-off-by:
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Mirela Simonovic authored
GEM-related clock models were incorrect and are fixed as follows (documented below for GEM0, but the same holds for any GEM ID): - CLK_GEM0_REF_UNGATED represents clock that has DIV0/1 divisors and the multiplexer controllable in GEM0_REF_CTRL (CRL_APB). The ID of this clock is newly introduced in this patch. - CLK_GEM0_REF models the clock mux that selects the reference clock for Tx, i.e. selects CLK_GEM0_REF_UNGATED or external Tx clock. This mux is controllable via GEM_CLK_CTRL (IOU_SLCR), bit GEM0_REF_SRC_SEL. Note that the routing of external clock to the mux is not modelled and is assumed to be configured by the FSBL if required, and not changeable at runtime. The ID of this clock is introduced in this patch. - CLK_GEM0_TX models clock with only a gate that is controlled via bit 25 in GEM0_REF_CTRL (CRL_APB). The parent of this clock is CLK_GEM0_REF. The clock ID of CLK_GEM0_TX matches the previous ID value of CLK_GEM0_REF. This is done in order to fix the clock models and incorrect binding without requiring to change device-tree (binding of clock IDs to GEM interface). - CLK_GEM0_RX models clock that has only gate controlled via RX_CLKACT bit (26) in GEM0_REF_CTRL (CRL_APB). Parent of this clock is sourced from external RGMII PHY (via MIO or EMIO). We do not model the whole clock path to the Rx gate, since this is configured by the FSBL and never changed at runtime (and there is no mechanism to change the path at runtime). The clock ID of CLK_GEM0_RX clock is equal to the previous ID value of CLK_GEM0_TX clock. This is done because the TX/RX were swapped in device tree, so by fixing the IDs this way there is no need for device tree fix. Rates of the external RX/TX clocks can be specified in device tree if needed. Right now, that's not necessary because Tx clock is sourced from an on-chip PLL (via CLK_GEM0_REF_UNGATED/CLK_GEM0_REF), whereas the Rx clock is sourced from external reference and the driver never attempts to get/get clock rate (only to enable it). If this changes in future, ATF clock model doesn't need to be changed. Instead, the clock rates for gem0_tx_ext and gem0_rx_ext have to be specified in device tree. Signed-off-by:
Will Wong <will.wong@xilinx.com> Signed-off-by:
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Mounika Grace Akula authored
This patch renames FPD WDT clock ID from CLK_WDT to CLK_FPD_WDT. Signed-off-by:
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- 19 Nov, 2019 1 commit
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Justin Chadwell authored
-Wlogical-op prevents common errors with using numerical constants where a boolean one is expected as well as when the operands of a logical operator are the same. While these are perfectly valid behavior, they can be a sign that something is slightly off. This patch adds this warning to gcc and it's closest equivalent to clang, while also fixing any warnings that enabling them causes. Change-Id: Iabadfc1e6ee0c44eef6685a23b0aed8abef8ce89 Signed-off-by:Justin Chadwell <justin.chadwell@arm.com>
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- 08 Mar, 2019 1 commit
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Luca Ceresoli authored
Allow EL2 (e.g. U-Boot) to load the configuration object at runtime into the Xilinx ZynqMP PMU firmware. This allows booting with U-Boot and U-Boot SPL with PMU FW without hard-coding the configuration object. Signed-off-by:Luca Ceresoli <luca@lucaceresoli.net>
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- 09 Jan, 2019 7 commits
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Jolly Shah authored
pm_service ipi functions can be used by other xilinx platforms. So move it to common directory. Also change node_id member type in pm_proc structure so it can be used for versal where device IDs are used instead of node IDs. To accommodate this change header files are re-organized. Signed-off-by:
Jolly Shah <jollys@xilinx.com>
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Jolly Shah authored
ZynqMP pm_service ipi file uses platform specific macros names. pm_service ipi functions can be used by other Xilinx platforms also. Make rename macros to use generic names so that it can be used by common file. pm_service ipi functions will be moved to common file in next patch. Signed-off-by:
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Jolly Shah authored
Use generic name for pm_api structure member, so that pm_api structure can be used other Xilinx platforms. Structure definition will be moved to common file in upcoming patch. Signed-off-by:
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Jolly Shah authored
ipi_mb functions can be used for other Xilinx platform. Move it to common file from platform specific files. Signed-off-by:
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Jolly Shah authored
Move zynqmp_ipi.h to platform specific include directory. Rename it to plat_ipi.h instead of platform name. So, it can be used to common source files which needs platform specific data. Signed-off-by:
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Jolly Shah authored
Move zynqmp_def.h to platform specific include directory. Also, update source file to include header file from updated path of zynqmp_def.h Signed-off-by:
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Jolly Shah authored
Move zynqmp_private.h to platform specific include directory. Also, rename it to plat_private.h instead of having platform name. So, it can be used to common source files which needs platform specific data. Signed-off-by:
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- 04 Jan, 2019 13 commits
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Jolly Shah authored
This clock does not drive any clock in LPD so there is no need for Linux to try to initialize it. Signed-off-by:
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Jolly Shah authored
Linux has no reason to use these system and debug clocks and therefore shouldn't access them. These clocks are marked as invalid in order to prevent Linux from registering and querying them. Note that despite clocks being marked as invalid a security issue still remains in place as there is nothing that prevents the non-secure world from gating these clocks and that way causing damage to the system. Signed-off-by:
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Jolly Shah authored
These clocks are marked as invalid in order to prevent Linux from registering them. Note that despite clocks being marked as invalid a security issue still remains in place as there is nothing that prevents the non-secure world from gating these clocks and that way halt the whole APU subsystem. Signed-off-by:
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Jolly Shah authored
In the existing model for ACPU clock the mux, divider, and gate were represented as one clock and ACPU_HALF was modelled as child of ACPU clock. This is not correct. ACPU clock model contains only mux and the divider, and it has 2 children: ACPU_FULL and ACPU_HALF clocks which have only gates. The models of ACPU and ACPU_HALF clocks are fixed and ACPU_FULL clock is added. Signed-off-by:
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Jolly Shah authored
Clock get parent EEMI API is reimplemented to use system-level clock and pll EEMI APIs rather than direct MMIO read/write accesses to clock and pll control registers. Since linux still uses clock set parent API to get pre_src, post_src, div2 and bypasss, in the implementation of pm_clock_get_parent() we need to workaround this by distinguishing two cases: 1) if the given clock ID corresponds to a PLL-related clock ID (*_PRE_SRC, *_POST_SRC, *_INT_MUX or *_PLL clock IDs); or 2) given clock ID is truly an on-chip clock. For case 1) we'll map the call onto PLL-specific EEMI API with the respective parameter ID. For case 2) the call is passed to the PMU. Signed-off-by:
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Jolly Shah authored
Clock set parent EEMI API is reimplemented to use system-level clock and pll EEMI APIs rather than direct MMIO read/write accesses to clock and pll control registers. Since linux still uses clock set parent API to set pre_src, post_src, div2 and bypass, in the implementation of pm_clock_set_parent() we need to workaround this by distinguishing two cases: 1) if the given clock ID corresponds to a PLL-related clock ID (*_PRE_SRC, *_POST_SRC, *_INT_MUX or *PLL clock IDs); or 2) given clock ID is truly an on-chip clock. For case 1) we'll map the call onto PLL set parameter EEMI API with the respective parameter ID. Since clock set parent interface to EL1/2 receives parent index (mux select value), the value is just passed to PMU. Functions that appear to be unused after this change is made are removed. Setting the parent of *PLL clocks, that actually model bypass, is not possible. This is already ensured by the existing clock model having the CLK_SET_RATE_NO_REPARENT flag. The API also doesn't allow changing the bypass parent. Bypass is controlled only by the PMU firmware. Signed-off-by:
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Jolly Shah authored
Clock set/get rate are not implemented and will likely never be. Remove empty function stubs. Signed-off-by:
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Jolly Shah authored
Clock get divider EEMI API is reimplemented to use system-level clock get divider EEMI API rather than direct MMIO read/write accesses to clock control registers. Signed-off-by:
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Jolly Shah authored
Clock set divider EEMI API is reimplemented to use system-level clock set divider EEMI API rather than direct MMIO read/write accesses to clock control registers. Signed-off-by:
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Jolly Shah authored
Clock get state EEMI API is reimplemented to use system-level clock and pll EEMI APIs rather than direct MMIO read/write accesses to clock and pll control registers. Since linux is_enabled method for PLLs still uses clock get state API get the PLL state, in the implementation of pm_clock_getstate() we need to workaround this by distinguishing two cases: 1) if the given clock ID corresponds to a PLL output clock ID; or 2) given clock ID is truly an on-chip clock whose state of the gate should be returned. For case 1) we'll call pm_api_clock_pll_getstate() implemented in pm_api_clock.h/c. This function will query the PLL state from PMU using the system-level PLL get mode EEMI API. For case 2) we'll call the PMU to query the clock gate state using system-level clock get status EEMI API. Functions that appear to be unused after this change is made are removed. Signed-off-by:
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Jolly Shah authored
Clock disable EEMI API is reimplemented to use system-level clock and pll EEMI APIs rather than direct MMIO read/write accesses to clock and pll control registers. Since linux still uses clock disable API to reset the PLL in the implementation of pm_clock_disable() we need to workaround this by distinguishing two cases: 1) if the given clock ID corresponds to a PLL output clock ID; or 2) given clock ID is truly an on-chip clock that can be gated. For case 1) we'll call pm_api_clock_pll_disable() implemented in pm_api_clock.h/c. This function will reset the PLL using the system-level PLL set mode EEMI API with the reset mode argument. For case 2) we'll call the PMU to configure the clock gate. This is done using system-level clock disable EEMI API. Functions that appear to be unused after this change is made are removed. Signed-off-by:
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Jolly Shah authored
Clock enable EEMI API is reimplemented to use system-level clock and pll EEMI APIs rather than direct MMIO read/write accesses to clock and pll control registers. Since linux still uses clock enable API to trigger locking of the PLLs in the pm_clock_enable() implementation we need to workaround this by distinguishing two cases: 1) if the given clock ID corresponds to a PLL output clock ID; or 2) given clock ID is truly an on-chip clock that can be gated. For case 1) we'll call pm_api_clock_pll_enable() implemented in pm_api_clock.h/c. This function checks what is the buffered PLL mode and calls the system-level PLL set mode EEMI API with the buffered mode value specified as argument. Long term, if linux driver get fixed to use PLL EEMI API to control PLLs, this case could be removed from ATF. For case 2) we'll call the PMU to configure the clock gate. This is done using system-level clock enable EEMI API. Signed-off-by:
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Jolly Shah authored
When linux calls pm_ioctl_get_pll_frac_mode() it doesn't expect the actual mode to be read from hardware, but the value that it is intending to program. Therefore, we return the buffered value to linux. Signed-off-by:
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