- 09 Oct, 2020 1 commit
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Jimmy Brisson authored
And from crash_console_flush. We ignore the error information return by console_flush in _every_ place where we call it, and casting the return type to void does not work around the MISRA violation that this causes. Instead, we collect the error information from the driver (to avoid changing that API), and don't return it to the caller. Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1 Signed-off-by:
Jimmy Brisson <jimmy.brisson@arm.com>
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- 22 May, 2019 1 commit
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Andrew F. Davis authored
The Cortex-A72 based cores on K3 platforms can be clocked fast enough that an extra latency cycle is needed to ensure correct L2 access. Set the latency here for all A72 cores. Signed-off-by:
Andrew F. Davis <afd@ti.com> Change-Id: Id534316dec1c1f326908efbfd964f219cda7386a
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- 30 Apr, 2019 1 commit
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Andrew F. Davis authored
The MSMC port defines were added to help in the case when some ports are not connected and have no cores attached. We can get the same functionality by defined the number of cores on that port to zero. This simplifies several code paths, do this here. Signed-off-by:
Andrew F. Davis <afd@ti.com> Change-Id: I3247fe37af7b86c3227e647b4f617fab70c8ee8a
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- 25 Oct, 2018 1 commit
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Antonio Nino Diaz authored
Even though at this point plat_crash_console_flush is optional, it will stop being optional in a following patch. The console driver of warp7 doesn't support flush, so the implementation is a placeholder. TI had ``plat_crash_console_init`` and ``plat_crash_console_putc``, but they weren't global so they weren't actually used. Also, they were calling the wrong functions. imx8_helpers.S only has placeholders for all of the functions. Change-Id: I8d17bbf37c7dad74e134c61ceb92acb9af497718 Signed-off-by:
Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 19 Jun, 2018 2 commits
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Nishanth Menon authored
Signed-off-by:
Nishanth Menon <nm@ti.com> Signed-off-by:
Benjamin Fair <b-fair@ti.com> Signed-off-by:
Andrew F. Davis <afd@ti.com>
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Benjamin Fair authored
The K3 family of SoCs has multiple interconnects. The key interconnect for high performance processors is the MSMC3 interconnect. This is an io-coherent interconnect which exports multiple ports for each processor cluster. Sometimes, port 0 of the MSMC may not have an ARM cluster OR is isolated such that the instance of ATF does not manage it. Define macros in platform_def.h to help handle this. Signed-off-by:
Benjamin Fair <b-fair@ti.com> Signed-off-by:
Nishanth Menon <nm@ti.com> Signed-off-by:
Andrew F. Davis <afd@ti.com>
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