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Correct function header of pm_api_clock_getparent() and
pm_api_clock_setparent().
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Acked-by: Will Wong <WILLW@xilinx.com>

PLL type clock is enabled by FSBL on boot-up. PMUFW enable/disable
them based on their user count. So, it should not be handled from ATF.

Put PLL type clock into bypass and reset mode only while changing
PLL rate (FBDIV).
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

This patch adds new API's for performing pl configuration
readback.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

CCF has already provision to enable clock during registration
through CLK_IS_CRITICAL flag. Use CLK_IS_CRITICAL instead of
init_enable attribute.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Jolly Shah <jolly.shah@xilinx.com>

WDT used by APU is FPD_WDT. FPD WDT clock is controlled by
FPD_SLCR.WDT_CLK_SEL register. Correct the same in WDT clock
database.

As per FPD_SLCR.WDT_CLK_SEL register, there can be only two
parents of WDT clock not three. Fix the same by correcting it's
parents in clock database.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Jolly Shah <jolly.shah@xilinx.com>

Add support for writing to AFI registers.
So that after writing a bitstream the interface can be programmed.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

Since the MMIO read/write APIs are removed from Linux user space,
Linux cannot directly write to the Global General Storage Register 4
any more to set healthy boot status.

Create an IOCTL to allow Linux to set boot health status.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Will Wong <willw@xilinx.com>

To make ULPI transceiver work, a HIGH - LOW - HIGH pulse needs
to be given to resetb pin of ULPI chip. In ZYNQMP, this resetb
pin is being driven by BOOT MODE PIN 1. The BOOT MODE PIN's
are controlled by BOOT_PIN_CTRL register present in CRL_APB
address region. Since CRL_APB can be resticted to secure access,
this pin should be controlled by ATF.

This patch adds the support for the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

Change-Id: I908844364bf8080612aaa6d750d7d2441ecc2eb8
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

- add svc configuration according to values burnt
  to the chip efuse

Change-Id: Icf5d7cc41bc09ac2244d0a126106e681afebb064
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

Some customers are missing host libraries required for doimage
builds.
This patch requests for the library installation check for every
doimage build and suggest the required installation steps in case
of missing headers.

Change-Id: Icde18c3d4d6045f65e50d2dc9e6514971f40033e
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>

This patch enables handling PMU overflow IRQ by GIC SPI's
directly in EL3. Also implement additional SMC routine,
which can disable the solution on demand in runtime.

Since it is possible to configure PMU interrupt trigger type
in the MADT ACPI table, it is enough to set it only once in EL3
during initialization.

Change-Id: Ie76aa62ccc4fd7cabfec9e3d5ed9970ada1c1b2a
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

Current default behavior of cpu_standby callback
is problematic during the SBSA test, which is
unable to run due to EL3 panic. Make it dependent on
the PM firmware running.

Change-Id: I7a53de8c880bd23b157dd65ce14bb48b5a5c76c8
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

In order to allow the use of PCIe cards such as graphics cards, whose
demands for BAR space are typically much higher than those of network
or SATA/USB cards, reconfigure the I/O windows so we can declare two
MMIO PCI regions: a 512 MB MMIO32 one at 0xc000_0000 and a 4 GB MMIO64
one at 0x8_0000_0000. In addition, this will leave ample room for an
ECAM config space at 0xe000_0000 (up to the ECAM maximum of 256 MB)

For compatibility with older kernels or firmware, leave the original
16 MB window in place as well.

Change-Id: Ia8177194e542078772f90941eced81b231c16887
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

In order to allow the use of PCIe cards such as graphics cards, whose
demands for BAR space are typically much higher than those of network
or SATA/USB cards, reconfigure the I/O windows so we can declare two
MMIO PCI regions: a 512 MB MMIO32 one at 0xc000_0000 and a 4 GB MMIO64
one at 0x8_0000_0000. In addition, this will leave ample room for an
ECAM config space at 0xe000_0000 (up to the ECAM maximum of 256 MB)

For compatibility with older kernels or firmware, leave the original
16 MB window in place as well.

Change-Id: I80b00691ae8d0a3f3f7285b8e0bfc21c0a095e94
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

Define the RT service space as secure with use of memory controller
trustzone feature. Thanks to this protection, any NS-Bootloader nor NS-OS,
won't be able to access RT services (e.g. accidentally overwrite it,
which will at best result in RT services unavailability).

Change-Id: Ie5b6cbe9a1b77879d6d8f8eac5d4e41e468496ce
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

Rename a8k_common.h to armada_common.h to keep the same header
name across all other Marvell Armada platforms.
This is especially useful since various Marvell platforms may
use common platform files and share the driver modules.

Change-Id: I7262105201123d54ccddef9aad4097518f1e38ef
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

Use TI-SCI messages to request core power down from system controller
firmware.
Signed-off-by: Andrew F. Davis <afd@ti.com>

Add another level of abstraction of weak defs for
arm_bl2_handle_post_image_load to prevent two weak definitions
of the same function

Change-Id: Ie953786f43b0f88257c82956ffaa5fe0d19603db
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

No functional changes.

Change-Id: I850f08718abb69d5d58856b0e3de036266d8c2f4
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Change-Id: I5993b425445ee794e6d2a792c244c0af53640655
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Change-Id: I11509a3271d7608048d49e7dd5192be0c2a313f0
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Currently in Linux maximum number of clocks is hard-coded and
so it needs to allocate static memory. It can get actual clock
number after querying all clock names by special clock name
string. Add new query data parameter to get actual number of
clocks so Linux can get actual clock numbers in advance.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>

Small patch which removes some redundant casts to (void *).

Change-Id: If1cfd68f2989bac1d39dbb3d1c31d4119badbc21
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Use TI-SCI messages to request reset from system controller firmware.
Signed-off-by: Andrew F. Davis <afd@ti.com>

Use TI-SCI messages to request core start from system controller
firmware.
Signed-off-by: Andrew F. Davis <afd@ti.com>

TI-SCI message protocol provides support for controlling of various
physical cores available in the SoC. In order to control which host is
capable of controlling a physical processor core, there is a processor
access control list that needs to be populated as part of the board
configuration data.

Introduce support for the set of TI-SCI message protocol APIs that
provide us with this capability of controlling physical cores.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>

Since system controller now has control over SoC power management, core
operation such as reset need to be explicitly requested to reboot the SoC.
Add support for this here.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>

TI-SCI message protocol provides support for management of various
hardware entities within the SoC.

In general, we expect to function at a device level of abstraction,
however, for proper operation of hardware blocks, many clocks directly
supplying the hardware block needs to be queried or configured.

Introduce support for the set of TI-SCI message protocol support that
provide us with this capability.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>

TI-SCI message protocol provides support for management of various
hardware entitites within the SoC.

We introduce the fundamental device management capability support to
the driver protocol as part of this change.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>

Texas Instrument's System Control Interface (TI-SCI) Message Protocol
is used in Texas Instrument's System on Chip (SoC) such as those
in K3 family AM654x SoCs to communicate between various compute
processors with a central system controller entity.

TI-SCI message protocol provides support for management of various
hardware entities within the SoC. Add support driver to allow
communication with system controller entity within the SoC.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>

Secure Proxy module manages hardware threads that are meant
for communication between the processor entities. Add support
for this here.
Signed-off-by: Andrew F. Davis <afd@ti.com>

tf_printf and tf_snprintf are now called printf and snprintf, so the
code needs to be updated.

Change-Id: Iffeee97afcd6328c4c2d30830d4923b964682d71
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

The codebase was using non-standard headers. It is needed to replace
them by the correct ones so that we can use the new libc headers.

Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

All the arm platforms were including the files related to
mem-protect. This configuration generates some problems
with new platforms that don't support such functionality,
and for that reason this patch moves these files to the
platform specific makefiles.

Change-Id: I6923e5224668b76667795d8e11723cede7979b1e
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

These changes address most of the required MISRA rules. In the process,
some from generic code is also fixed.

No functional changes.

Change-Id: I707dbec9b34b802397e99da2f5ae738165d6feba
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

Move from bl31_early_platform_setup to bl31_early_platform_setup2
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

Change-Id: If53b5b2430a06ce8cf6e7948765b560b37afc335
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

The Raspberry Pi 3 port doesn't actually depend on any Arm platform
code, so the dependencies can be removed.

Change-Id: Ic2f47f5001bebde3862815b1d880a169d82b3f65
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

This function is required for platforms where
COLD_BOOT_SINGLE_CPU=0 however it was missing from rockchip
platforms

Change-Id: I32a85f226a4f22085a27113903f34bdb6f28dbcc
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>