1. 22 May, 2014 6 commits
    • Achin Gupta's avatar
      Introduce interrupt registration framework in BL3-1 · e1333f75
      Achin Gupta authored
      This patch introduces a framework for registering interrupts routed to
      EL3. The interrupt routing model is governed by the SCR_EL3.IRQ and
      FIQ bits and the security state an interrupt is generated in. The
      framework recognizes three type of interrupts depending upon which
      exception level and security state they should be handled in
      i.e. Secure EL1 interrupts, Non-secure interrupts and EL3
      interrupts. It provides an API and macros that allow a runtime service
      to register an handler for a type of interrupt and specify the routing
      model. The framework validates the routing model and uses the context
      management framework to ensure that it is applied to the SCR_EL3 prior
      to entry into the target security state. It saves the handler in
      internal data structures. An API is provided to retrieve the handler
      when an interrupt of a particular type is asserted. Registration is
      expected to be done once by the primary CPU. The same handler and
      routing model is used for all CPUs.
      
      Support for EL3 interrupts will be added to the framework in the
      future. A makefile flag has been added to allow the FVP port choose
      between ARM GIC v2 and v3 support in EL3. The latter version is
      currently unsupported.
      
      A framework for handling interrupts in BL3-1 will be introduced in
      subsequent patches. The default routing model in the absence of any
      handlers expects no interrupts to be routed to EL3.
      
      Change-Id: Idf7c023b34fcd4800a5980f2bef85e4b5c29e649
      e1333f75
    • Achin Gupta's avatar
      Add context library API to change a bit in SCR_EL3 · c429b5e9
      Achin Gupta authored
      This patch adds an API to write to any bit in the SCR_EL3 member of
      the 'cpu_context' structure of the current CPU for a specified
      security state. This API will be used in subsequent patches which
      introduce interrupt management in EL3 to specify the interrupt routing
      model when execution is not in EL3.
      
      It also renames the cm_set_el3_elr() function to cm_set_elr_el3()
      which is more in line with the system register name being targeted by
      the API.
      
      Change-Id: I310fa7d8f827ad3f350325eca2fb28cb350a85ed
      c429b5e9
    • Vikram Kanigiri's avatar
      Add support for BL3-1 as a reset vector · dbad1bac
      Vikram Kanigiri authored
      This change adds optional reset vector support to BL3-1
      which means BL3-1 entry point can detect cold/warm boot,
      initialise primary cpu, set up cci and mail box.
      
      When using BL3-1 as a reset vector it is assumed that
      the BL3-1 platform code can determine the location of
      the BL3-2 images, or load them as there are no parameters
      that can be passed to BL3-1 at reset.
      
      It also fixes the incorrect initialisation of mailbox
      registers on the FVP platform
      
      This feature can be enabled by building the code with
      make variable RESET_TO_BL31 set as 1
      
      Fixes ARM-software/TF-issues#133
      Fixes ARM-software/TF-issues#20
      
      Change-Id: I4e23939b1c518614b899f549f1e8d412538ee570
      dbad1bac
    • Vikram Kanigiri's avatar
      Rework memory information passing to BL3-x images · 6871c5d3
      Vikram Kanigiri authored
      The issues addressed in this patch are:
      
      1. Remove meminfo_t from the common interfaces in BL3-x,
      expecting that platform code will find a suitable mechanism
      to determine the memory extents in these images and provide
      it to the BL3-x images.
      
      2. Remove meminfo_t and bl31_plat_params_t from all FVP BL3-x
      code as the images use link-time information to determine
      memory extents.
      
      meminfo_t is still used by common interface in BL1/BL2 for
      loading images
      
      Change-Id: I4e825ebf6f515b59d84dc2bdddf6edbf15e2d60f
      6871c5d3
    • Vikram Kanigiri's avatar
      Populate BL31 input parameters as per new spec · 4112bfa0
      Vikram Kanigiri authored
      This patch is based on spec published at
      https://github.com/ARM-software/tf-issues/issues/133
      
      It rearranges the bl31_args struct into
      bl31_params and bl31_plat_params which provide the
      information needed for Trusted firmware and platform
      specific data via x0 and x1
      
      On the FVP platform BL3-1 params and BL3-1 plat params
      and its constituents are stored at the start of TZDRAM.
      
      The information about memory availability and size for
      BL3-1, BL3-2 and BL3-3 is moved into platform specific data.
      
      Change-Id: I8b32057a3d0dd3968ea26c2541a0714177820da9
      4112bfa0
    • Vikram Kanigiri's avatar
      Rework handover interface between BL stages · 29fb905d
      Vikram Kanigiri authored
      This patch reworks the handover interface from: BL1 to BL2 and
      BL2 to BL3-1. It removes the raise_el(), change_el(), drop_el()
      and run_image() functions as they catered for code paths that were
      never exercised.
      BL1 calls bl1_run_bl2() to jump into BL2 instead of doing the same
      by calling run_image(). Similarly, BL2 issues the SMC to transfer
      execution to BL3-1 through BL1 directly. Only x0 and x1 are used
      to pass arguments to BL31. These arguments and parameters for
      running BL3-1 are passed through a reference to a
      'el_change_info_t' structure. They were being passed value in
      general purpose registers earlier.
      
      Change-Id: Id4fd019a19a9595de063766d4a66295a2c9307e1
      29fb905d
  2. 16 May, 2014 2 commits
    • Jeenu Viswambharan's avatar
      Add build configuration for timer save/restore · 2da8d8bf
      Jeenu Viswambharan authored
      At present, non-secure timer register contents are saved and restored as
      part of world switch by BL3-1. This effectively means that the
      non-secure timer stops, and non-secure timer interrupts are prevented
      from asserting until BL3-1 switches back, introducing latency for
      non-secure services. Often, secure world might depend on alternate
      sources for secure interrupts (secure timer or platform timer) instead
      of non-secure timers, in which case this save and restore is
      unnecessary.
      
      This patch introduces a boolean build-time configuration NS_TIMER_SWITCH
      to choose whether or not to save and restore non-secure timer registers
      upon world switch. The default choice is made not to save and restore
      them.
      
      Fixes ARM-software/tf-issues#148
      
      Change-Id: I1b9d623606acb9797c3e0b02fb5ec7c0a414f37e
      2da8d8bf
    • Soby Mathew's avatar
      Rework BL3-1 unhandled exception handling and reporting · a43d431b
      Soby Mathew authored
      This patch implements the register reporting when unhandled exceptions are
      taken in BL3-1. Unhandled exceptions will result in a dump of registers
      to the console, before halting execution by that CPU. The Crash Stack,
      previously called the Exception Stack, is used for this activity.
      This stack is used to preserve the CPU context and runtime stack
      contents for debugging and analysis.
      
      This also introduces the per_cpu_ptr_cache, referenced by tpidr_el3,
      to provide easy access to some of BL3-1 per-cpu data structures.
      Initially, this is used to provide a pointer to the Crash stack.
      
      panic() now prints the the error file and line number in Debug mode
      and prints the PC value in release mode.
      
      The Exception Stack is renamed to Crash Stack with this patch.
      The original intention of exception stack is no longer valid
      since we intend to support several valid exceptions like IRQ
      and FIQ in the trusted firmware context. This stack is now
      utilized for dumping and reporting the system state when a
      crash happens and hence the rename.
      
      Fixes ARM-software/tf-issues#79 Improve reporting of unhandled exception
      
      Change-Id: I260791dc05536b78547412d147193cdccae7811a
      a43d431b
  3. 08 May, 2014 1 commit
    • Soby Mathew's avatar
      Preserve x19-x29 across world switch for exception handling · c3260f9b
      Soby Mathew authored
      Previously exception handlers in BL3-1, X19-X29 were not saved
      and restored on every SMC/trap into EL3. Instead these registers
      were 'saved as needed' as a side effect of the A64 ABI used by the C
      compiler.
      
      That approach failed when world switching but was not visible
      with the TSP/TSPD code because the TSP is 64-bit, did not
      clobber these registers when running and did not support pre-emption
      by normal world interrupts. These scenarios showed
      that the values in these registers can be passed through a world
      switch, which broke the normal and trusted world assumptions
      about these registers being preserved.
      
      The Ideal solution saves and restores these registers when a
      world switch occurs - but that type of implementation is more complex.
      So this patch always saves and restores these registers on entry and
      exit of EL3.
      
      Fixes ARM-software/tf-issues#141
      
      Change-Id: I9a727167bbc594454e81cf78a97ca899dfb11c27
      c3260f9b
  4. 07 May, 2014 3 commits
    • Andrew Thoelke's avatar
      Access system registers directly in assembler · 7935d0a5
      Andrew Thoelke authored
      Instead of using the system register helper functions to read
      or write system registers, assembler coded functions should
      use MRS/MSR instructions. This results in faster and more
      compact code.
      
      This change replaces all usage of the helper functions with
      direct register accesses.
      
      Change-Id: I791d5f11f257010bb3e6a72c6c5ab8779f1982b3
      7935d0a5
    • Andrew Thoelke's avatar
      Correct usage of data and instruction barriers · 8cec598b
      Andrew Thoelke authored
      The current code does not always use data and instruction
      barriers as required by the architecture and frequently uses
      barriers excessively due to their inclusion in all of the
      write_*() helper functions.
      
      Barriers should be used explicitly in assembler or C code
      when modifying processor state that requires the barriers in
      order to enable review of correctness of the code.
      
      This patch removes the barriers from the helper functions and
      introduces them as necessary elsewhere in the code.
      
      PORTING NOTE: check any port of Trusted Firmware for use of
      system register helper functions for reliance on the previous
      barrier behaviour and add explicit barriers as necessary.
      
      Fixes ARM-software/tf-issues#92
      
      Change-Id: Ie63e187404ff10e0bdcb39292dd9066cb84c53bf
      8cec598b
    • Andrew Thoelke's avatar
      Set processor endianness immediately after RESET · 40fd0725
      Andrew Thoelke authored
      SCTLR_EL3.EE is being configured too late in bl1_arch_setup() and
      bl31_arch_setup() after data accesses have already occured on
      the cold and warm boot paths.
      
      This control bit must be configured immediately on CPU reset to
      match the endian state of the firmware (little endian).
      
      Fixes ARM-software/tf-issues#145
      
      Change-Id: Ie12e46fbbed6baf024c30beb50751591bb8c8655
      40fd0725
  5. 06 May, 2014 6 commits
    • Dan Handley's avatar
      Remove variables from .data section · 625de1d4
      Dan Handley authored
      Update code base to remove variables from the .data section,
      mainly by using const static data where possible and adding
      the const specifier as required. Most changes are to the IO
      subsystem, including the framework APIs. The FVP power
      management code is also affected.
      
      Delay initialization of the global static variable,
      next_image_type in bl31_main.c, until it is realy needed.
      Doing this moves the variable from the .data to the .bss
      section.
      
      Also review the IO interface for inconsistencies, using
      uintptr_t where possible instead of void *. Remove the
      io_handle and io_dev_handle typedefs, which were
      unnecessary, replacing instances with uintptr_t.
      
      Fixes ARM-software/tf-issues#107.
      
      Change-Id: I085a62197c82410b566e4698e5590063563ed304
      625de1d4
    • Dan Handley's avatar
      Reduce deep nesting of header files · 97043ac9
      Dan Handley authored
      Reduce the number of header files included from other header
      files as much as possible without splitting the files. Use forward
      declarations where possible. This allows removal of some unnecessary
      "#ifndef __ASSEMBLY__" statements.
      
      Also, review the .c and .S files for which header files really need
      including and reorder the #include statements alphabetically.
      
      Fixes ARM-software/tf-issues#31
      
      Change-Id: Iec92fb976334c77453e010b60bcf56f3be72bd3e
      97043ac9
    • Dan Handley's avatar
      Always use named structs in header files · fb037bfb
      Dan Handley authored
      Add tag names to all unnamed structs in header files. This
      allows forward declaration of structs, which is necessary to
      reduce header file nesting (to be implemented in a subsequent
      commit).
      
      Also change the typedef names across the codebase to use the _t
      suffix to be more conformant with the Linux coding style. The
      coding style actually prefers us not to use typedefs at all but
      this is considered a step too far for Trusted Firmware.
      
      Also change the IO framework structs defintions to use typedef'd
      structs to be consistent with the rest of the codebase.
      
      Change-Id: I722b2c86fc0d92e4da3b15e5cab20373dd26786f
      fb037bfb
    • Dan Handley's avatar
      Remove vpath usage in makefiles · bee82417
      Dan Handley authored
      Remove all usage of the vpath keyword in makefiles as it was prone
      to mistakes. Specify the relative paths to source files instead.
      
      Also reorder source files in makefiles alphabetically.
      
      Fixes ARM-software/tf-issues#121
      
      Change-Id: Id15f60655444bae60e0e2165259efac71a50928b
      bee82417
    • Dan Handley's avatar
      Make use of user/system includes more consistent · 35e98e55
      Dan Handley authored
      Make codebase consistent in its use of #include "" syntax for
      user includes and #include <> syntax for system includes.
      
      Fixes ARM-software/tf-issues#65
      
      Change-Id: If2f7c4885173b1fd05ac2cde5f1c8a07000c7a33
      35e98e55
    • Dan Handley's avatar
      Move include and source files to logical locations · 4ecca339
      Dan Handley authored
      Move almost all system include files to a logical sub-directory
      under ./include. The only remaining system include directories
      not under ./include are specific to the platform. Move the
      corresponding source files to match the include directory
      structure.
      
      Also remove pm.h as it is no longer used.
      
      Change-Id: Ie5ea6368ec5fad459f3e8a802ad129135527f0b3
      4ecca339
  6. 15 Apr, 2014 1 commit
    • Andrew Thoelke's avatar
      Allocate single stacks for BL1 and BL2 · 2bf28e62
      Andrew Thoelke authored
      The BL images share common stack management code which provides
      one coherent and one cacheable stack for every CPU. BL1 and BL2
      just execute on the primary CPU during boot and do not require
      the additional CPU stacks. This patch provides separate stack
      support code for UP and MP images, substantially reducing the
      RAM usage for BL1 and BL2 for the FVP platform.
      
      This patch also provides macros for declaring stacks and
      calculating stack base addresses to improve consistency where
      this has to be done in the firmware.
      
      The stack allocation source files are now included via
      platform.mk rather than the common BLx makefiles. This allows
      each platform to select the appropriate MP/UP stack support
      for each BL image.
      
      Each platform makefile must be updated when including this
      commit.
      
      Fixes ARM-software/tf-issues#76
      
      Change-Id: Ia251f61b8148ffa73eae3f3711f57b1ffebfa632
      2bf28e62
  7. 08 Apr, 2014 2 commits
    • Sandrine Bailleux's avatar
      Define frequency of system counter in platform code · 9e86490f
      Sandrine Bailleux authored
      BL3-1 architecture setup code programs the system counter frequency
      into the CNTFRQ_EL0 register. This frequency is defined by the
      platform, though. This patch introduces a new platform hook that
      the architecture setup code can call to retrieve this information.
      In the ARM FVP port, this returns the first entry of the frequency
      modes table from the memory mapped generic timer.
      
      All system counter setup code has been removed from BL1 as some
      platforms may not have initialized the system counters at this stage.
      The platform specific settings done exclusively in BL1 have been moved
      to BL3-1. In the ARM FVP port, this consists in enabling and
      initializing the System level generic timer. Also, the frequency change
      request in the counter control register has been set to 0 to make it
      explicit it's using the base frequency. The CNTCR_FCREQ() macro has been
      fixed in this context to give an entry number rather than a bitmask.
      
      In future, when support for firmware update is implemented, there
      is a case where BL1 platform specific code will need to program
      the counter frequency. This should be implemented at that time.
      
      This patch also updates the relevant documentation.
      
      It properly fixes ARM-software/tf-issues#24
      
      Change-Id: If95639b279f75d66ac0576c48a6614b5ccb0e84b
      9e86490f
    • Sandrine Bailleux's avatar
      Revert "Move architecture timer setup to platform-specific code" · 65a9c0e9
      Sandrine Bailleux authored
      This reverts commit 1c297bf0
      because it introduced a bug: the CNTFRQ_EL0 register was no
      longer programmed by all CPUs.  bl31_platform_setup() function
      is invoked only in the cold boot path and consequently only
      on the primary cpu.
      
      A subsequent commit will correctly implement the necessary changes
      to the counter frequency setup code.
      
      Fixes ARM-software/tf-issues#125
      
      Conflicts:
      
      	docs/firmware-design.md
      	plat/fvp/bl31_plat_setup.c
      
      Change-Id: Ib584ad7ed069707ac04cf86717f836136ad3ab54
      65a9c0e9
  8. 26 Mar, 2014 4 commits
    • Andrew Thoelke's avatar
      Place assembler functions in separate sections · 0a30cf54
      Andrew Thoelke authored
      This extends the --gc-sections behaviour to the many assembler
      support functions in the firmware images by placing each function
      into its own code section. This is achieved by creating a 'func'
      macro used to declare each function label.
      
      Fixes ARM-software/tf-issues#80
      
      Change-Id: I301937b630add292d2dec6d2561a7fcfa6fec690
      0a30cf54
    • Andrew Thoelke's avatar
      Use --gc-sections during link · dccc537a
      Andrew Thoelke authored
      All common functions are being built into all binary images,
      whether or not they are actually used. This change enables the
      use of -ffunction-sections, -fdata-sections and --gc-sections
      in the compiler and linker to remove unused code and data from
      the images.
      
      Change-Id: Ia9f78c01054ac4fa15d145af38b88a0d6fb7d409
      dccc537a
    • Sandrine Bailleux's avatar
      Separate out BL2, BL3-1 and BL3-2 early exception vectors from BL1 · 6c595b3d
      Sandrine Bailleux authored
      bl1/aarch64/early_exceptions.S used to be re-used by BL2, BL3-1 and
      BL3-2.  There was some early SMC handling code in there that was not
      required by the other bootloader stages.  Therefore this patch
      introduces an even simpler exception vector source file for BL2,
      BL3-1 and BL3-2.
      
      Fixes ARM-software/tf-issues#38
      
      Change-Id: I0244b80e9930b0f8035156a0bf91cc3e9a8f995d
      6c595b3d
    • Vikram Kanigiri's avatar
      Move per cpu exception stack in BL31 to tzfw_normal_stacks · d8b07aa0
      Vikram Kanigiri authored
      Fixes ARM-software/tf-issues#70
      
      Change-Id: I7f024f173fbdecd315076f528b05d6295aff7276
      d8b07aa0
  9. 21 Mar, 2014 1 commit
    • Vikram Kanigiri's avatar
      Remove partially qualified asm helper functions · 6ba0b6d6
      Vikram Kanigiri authored
      Each ARM Trusted Firmware image should know in which EL it is running
      and it should use the corresponding register directly instead of reading
      currentEL and knowing which asm register to read/write
      
      Change-Id: Ief35630190b6f07c8fbb7ba6cb20db308f002945
      6ba0b6d6
  10. 20 Mar, 2014 2 commits
    • Jeenu Viswambharan's avatar
      Specify image entry in linker script · 9f98aa1a
      Jeenu Viswambharan authored
      At present, the entry point for each BL image is specified via the
      Makefiles and provided on the command line to the linker. When using a
      link script the entry point should rather be specified via the ENTRY()
      directive in the link script.
      
      This patch updates linker scripts of all BL images to specify the entry
      point using the ENTRY() directive. It also removes the --entry flag
      passed to the linker through Makefile.
      
      Fixes issue ARM-software/tf-issues#66
      
      Change-Id: I1369493ebbacea31885b51185441f6b628cf8da0
      9f98aa1a
    • Jeenu Viswambharan's avatar
      Implement ARM Standard Service · 64f6ea9b
      Jeenu Viswambharan authored
      This patch implements ARM Standard Service as a runtime service and adds
      support for call count, UID and revision information SMCs. The existing
      PSCI implementation is subsumed by the Standard Service calls and all
      PSCI calls are therefore dispatched by the Standard Service to the PSCI
      handler.
      
      At present, PSCI is the only specification under Standard Service. Thus
      call count returns the number of PSCI calls implemented. As this is the
      initial implementation, a revision number of 0.1 is returned for call
      revision.
      
      Fixes ARM-software/tf-issues#62
      
      Change-Id: I6d4273f72ad6502636efa0f872e288b191a64bc1
      64f6ea9b
  11. 10 Mar, 2014 1 commit
    • Jeenu Viswambharan's avatar
      Move architecture timer setup to platform-specific code · 1c297bf0
      Jeenu Viswambharan authored
      At present, bl1_arch_setup() and bl31_arch_setup() program the counter
      frequency using a value from the memory mapped generic timer. The
      generic timer however is not necessarily present on all ARM systems
      (although it is architected to be present on all server systems).
      
      This patch moves the timer setup to platform-specific code and updates
      the relevant documentation. Also, CNTR.FCREQ is set as the specification
      requires the bit corresponding to the counter's frequency to be set when
      enabling. Since we intend to use the base frequency, set bit 8.
      
      Fixes ARM-software/tf-issues#24
      
      Change-Id: I32c52cf882253e01f49056f47c58c23e6f422652
      1c297bf0
  12. 05 Mar, 2014 2 commits
    • Jon Medhurst's avatar
      Generate build time and date message at link time. · fb052462
      Jon Medhurst authored
      
      
      So it updates each time a bootloader changes, not just when bl*_main.c
      files are recompiled.
      
      Fixes ARM-software/tf-issues#33
      
      Change-Id: Ie8e1a7bd7e1913d2e96ac268606284f76af8c5ab
      Signed-off-by: default avatarJon Medhurst <tixy@linaro.org>
      fb052462
    • Jon Medhurst's avatar
      Update Makefiles to get proper dependency checking working. · 6d55d109
      Jon Medhurst authored
      
      
      This change requires all platforms to now specify a list of source files
      rather than object files.
      
      New source files should preferably be specified by using the path as
      well and we should add this in the future for all files so we can remove
      use of vpath. This is desirable because vpath hides issues like the fact
      that BL2 currently pulls in a BL1 file bl1/aarch64/early_exceptions.S
      and if in the future we added bl2/aarch64/early_exceptions.S then it's
      likely only one of the two version would be used for both bootloaders.
      
      This change also removes the 'dump' build target and simply gets
      bootloaders to always generate a dump file. At the same time the -x
      option is added so the section headers and symbols table are listed.
      
      Fixes ARM-software/tf-issues#11
      
      Change-Id: Ie38f7be76fed95756c8576cf3f3ea3b7015a18dc
      Signed-off-by: default avatarJon Medhurst <tixy@linaro.org>
      6d55d109
  13. 26 Feb, 2014 2 commits
    • Jeenu Viswambharan's avatar
      Remove duplicate xlat_table descriptions · e3fff153
      Jeenu Viswambharan authored
      The BL31 and BL2 linker scripts ended up having duplicate descriptions
      for xlat_tables section. This patch removes those duplicate
      descriptions.
      
      Change-Id: Ibbdda0902c57fca5ea4e91e0baefa6df8f0a9bb1
      e3fff153
    • Jeenu Viswambharan's avatar
      Implement late binding for runtime hooks · 7f366605
      Jeenu Viswambharan authored
      At present SPD power management hooks and BL3-2 entry are implemented
      using weak references. This would have the handlers bound and registered
      with the core framework at build time, but leaves them dangling if a
      service fails to initialize at runtime.
      
      This patch replaces implementation by requiring runtime handlers to
      register power management and deferred initialization hooks with the
      core framework at runtime. The runtime services are to register the
      hooks only as the last step, after having all states successfully
      initialized.
      
      Change-Id: Ibe788a2a381ef39aec1d4af5ba02376e67269782
      7f366605
  14. 20 Feb, 2014 6 commits
    • Achin Gupta's avatar
      Add power management support in the SPD · 607084ee
      Achin Gupta authored
      This patch implements a set of handlers in the SPD which are called by
      the PSCI runtime service upon receiving a power management
      operation. These handlers in turn pass control to the Secure Payload
      image if required before returning control to PSCI. This ensures that
      the Secure Payload has complete visibility of all power transitions in
      the system and can prepare accordingly.
      
      Change-Id: I2d1dba5629b7cf2d53999d39fe807dfcf3f62fe2
      607084ee
    • Achin Gupta's avatar
      Move PSCI to runtime services directory · 0a9f7473
      Achin Gupta authored
      This patch creates a 'services' directory and moves the PSCI under
      it. Other runtime services e.g. the Secure Payload Dispatcher service
      will be placed under the same directory in the future.
      
      Also fixes issue ARM-software/tf-issues#12
      
      Change-Id: I187f83dcb660b728f82155d91882e961d2255068
      0a9f7473
    • Achin Gupta's avatar
      Factor out translation table setup in ARM FVP port · a0cd989d
      Achin Gupta authored
      This patch factors out the ARM FVP specific code to create MMU
      translation tables so that it is possible for a boot loader stage to
      create a different set of tables instead of using the default ones.
      The default translation tables are created with the assumption that
      the calling boot loader stage executes out of secure SRAM. This might
      not be true for the BL3_2 stage in the future.
      
      A boot loader stage can define the `fill_xlation_tables()` function as
      per its requirements. It returns a reference to the level 1
      translation table which is used by the common platform code to setup
      the TTBR_EL3.
      
      This patch is a temporary solution before a larger rework of
      translation table creation logic is introduced.
      
      Change-Id: I09a075d5da16822ee32a411a9dbe284718fb4ff6
      a0cd989d
    • Achin Gupta's avatar
      Add support for BL3-2 in BL3-1 · 35ca3511
      Achin Gupta authored
      This patch adds the following support to the BL3-1 stage:
      
      1. BL3-1 allows runtime services to specify and determine the security
         state of the next image after BL3-1. This has been done by adding
         the `bl31_set_next_image_type()` & `bl31_get_next_image_type()`
         apis. The default security state is non-secure. The platform api
         `bl31_get_next_image_info()` has been modified to let the platform
         decide which is the next image in the desired security state.
      
      2. BL3-1 exports the `bl31_prepare_next_image_entry()` function to
         program entry into the target security state. It uses the apis
         introduced in 1. to do so.
      
      3. BL3-1 reads the information populated by BL2 about the BL3-2 image
         into its internal data structures.
      
      4. BL3-1 introduces a weakly defined reference `bl32_init()` to allow
         initialisation of a BL3-2 image. A runtime service like the Secure
         payload dispatcher will define this function if present.
      
      Change-Id: Icc46dcdb9e475ce6575dd3f9a5dc7a48a83d21d1
      35ca3511
    • Achin Gupta's avatar
      Rework BL2 to BL3-1 hand over interface · e4d084ea
      Achin Gupta authored
      This patch reworks BL2 to BL3-1 hand over interface by introducing a
      composite structure (bl31_args) that holds the superset of information
      that needs to be passed from BL2 to BL3-1.
      
        - The extents of secure memory available to BL3-1
        - The extents of memory available to BL3-2 (not yet implemented) and
          BL3-3
        - Information to execute BL3-2 (not yet implemented) and BL3-3 images
      
      This patch also introduces a new platform API (bl2_get_bl31_args_ptr)
      that needs to be implemented by the platform code to export reference to
      bl31_args structure which has been allocated in platform-defined memory.
      
      The platform will initialize the extents of memory available to BL3-3
      during early platform setup in bl31_args structure. This obviates the
      need for bl2_get_ns_mem_layout platform API.
      
      BL2 calls the bl2_get_bl31_args_ptr function to get a reference to
      bl31_args structure. It uses the 'bl33_meminfo' field of this structure
      to load the BL3-3 image. It sets the entry point information for the
      BL3-3 image in the 'bl33_image_info' field of this structure. The
      reference to this structure is passed to the BL3-1 image.
      
      Also fixes issue ARM-software/tf-issues#25
      
      Change-Id: Ic36426196dd5ebf89e60ff42643bed01b3500517
      e4d084ea
    • Jeenu Viswambharan's avatar
      Add exception vector guards · a7934d69
      Jeenu Viswambharan authored
      This patch adds guards so that an exception vector exceeding 32
      instructions will generate a compile-time error. This keeps the
      exception handlers in check from spilling over.
      
      Change-Id: I7aa56dd0071a333664e2814c656d3896032046fe
      a7934d69
  15. 17 Feb, 2014 1 commit
    • Jeenu Viswambharan's avatar
      Add support for handling runtime service requests · caa84939
      Jeenu Viswambharan authored
      
      
      This patch uses the reworked exception handling support to handle
      runtime service requests through SMCs following the SMC calling
      convention. This is a giant commit since all the changes are
      inter-related. It does the following:
      
      1. Replace the old exception handling mechanism with the new one
      2. Enforce that SP_EL0 is used C runtime stacks.
      3. Ensures that the cold and warm boot paths use the 'cpu_context'
         structure to program an ERET into the next lower EL.
      4. Ensures that SP_EL3 always points to the next 'cpu_context'
         structure prior to an ERET into the next lower EL
      5. Introduces a PSCI SMC handler which completes the use of PSCI as a
         runtime service
      
      Change-Id: I661797f834c0803d2c674d20f504df1b04c2b852
      Co-authored-by: default avatarAchin Gupta <achin.gupta@arm.com>
      caa84939