1. 14 Jul, 2017 1 commit
    • Jorge Ramirez-Ortiz's avatar
      Poplar: Initial commit for Poplar E-96Boards · e35d0edb
      Jorge Ramirez-Ortiz authored
      The board features the Hi3798C V200 with an integrated quad-core
      64-bit ARM Cortex A53 processor and high performance Mali T720 GPU,
      making it capable of running any commercial set-top solution based on
      Linux or Android. Its high performance specification also supports a
      premium user experience with up to H.265 HEVC decoding of 4K video at
      60 frames per second.
      
      SOC  Hisilicon Hi3798CV200
      CPU  Quad-core ARM Cortex-A53 64 bit
      DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB
      USB  Two USB 2.0 ports One USB 3.0 ports
      CONSOLE  USB-micro port for console support
      ETHERNET  1 GBe Ethernet
      PCIE  One PCIe 2.0 interfaces
      JTAG  8-Pin JTAG
      EXPANSION INTERFACE  Linaro 96Boards Low Speed Expansion slot
      DIMENSION Standard 160×120 mm 96Boards Enterprice Edition form factor
      WIFI  802.11AC 2*2 with Bluetooth
      CONNECTORS  One connector for Smart Card One connector for TSI
      
      The platform boot sequence is as follows:
          l-loader --> arm_trusted_firmware --> u-boot
      
      Rep...
      e35d0edb
  2. 10 Jul, 2017 4 commits
  3. 07 Jul, 2017 3 commits
  4. 06 Jul, 2017 7 commits
  5. 05 Jul, 2017 4 commits
  6. 02 Jul, 2017 1 commit
  7. 30 Jun, 2017 1 commit
    • Caesar Wang's avatar
      rockchip/rk3399: fixes the typo and the WARNINGS during suspend/resume · c3710ee7
      Caesar Wang authored
      
      
      This patch fixes the two things as follows:
      
      1) rk3399_flash_l2_b" seems to be a typo. That's "flush", not "flash".
      
      2) fixes the warnings log.
      We always hit the warnings thing during the suspend, as below log:
      ..
      [   51.022334] CPU5: shutdown
      [   51.025069] psci: CPU5 killed.
      INFO:    sdram_params->ddr_freq = 928000000
      WARNING: rk3399_flash_l2_b:reg 28830380,wait
      
      When the L2 completes the clean and invalidate sequence, it asserts the
      L2FLUSHDONE signal. The SoC can now deassert L2FLUSHREQ signal and then
      the L2 deasserts L2FLUSHDONE.
      
      Then, a loop without a delay isn't really great to measure time. We should
      probably add a udelay(10) or so in there and then maybe replace the WARN()
      after the loop. In the actual tests, the L2 cache will take ~4ms by
      default for big cluster.
      
      In the real world that give 10ms for the enough margin, like the
      ddr/cpu/cci frequency and other factors that will affect it.
      
      Change-Id: I55788c897be232bf72e8c7b0e10cf9b06f7aa50d
      Signed-off-by: default avatarCaesar Wang <wxt@rock-chips.com>
      c3710ee7
  8. 29 Jun, 2017 4 commits
  9. 28 Jun, 2017 15 commits