- 09 Jun, 2020 2 commits
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Andre Przywara authored
The only difference between GIC-500 and GIC-600 relevant to TF-A is the differing power management sequence. A certain GIC implementation is detectable at runtime, for instance by checking the IIDR register. Let's add that test before initiating the GIC-600 specific sequence, so the code can be used on both GIC-600 and GIC-500 chips alike, without deciding on a GIC chip at compile time. This means that the GIC-500 "driver" is now redundant. To allow minimal platform support, add a switch to disable GIC-600 support. Change-Id: I17ea97d9fb05874772ebaa13e6678b4ba3415557 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Manish Pandey authored
A new certificate "sip-sp-cert" has been added for Silicon Provider(SiP) owned Secure Partitions(SP). A similar support for Platform owned SP can be added in future. The certificate is also protected against anti- rollback using the trusted Non-Volatile counter. To avoid deviating from TBBR spec, support for SP CoT is only provided in dualroot. Secure Partition content certificate is assigned image ID 31 and SP images follows after it. The CoT for secure partition look like below. +------------------+ +-------------------+ | ROTPK/ROTPK Hash |------>| Trusted Key | +------------------+ | Certificate | | (Auth Image) | /+-------------------+ / | / | / | / | L v +------------------+ +-------------------+ | Trusted World |------>| SiP owned SPs | | Public Key | | Content Cert | +------------------+ | (Auth Image) | / +-------------------+ / | / v| +------------------+ L +-------------------+ | SP_PKG1 Hash |------>| SP_PKG1 | | | | (Data Image) | +------------------+ +-------------------+ . . . . . . +------------------+ +-------------------+ | SP_PKG8 Hash |------>| SP_PKG8 | | | | (Data Image) | +------------------+ +-------------------+ Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ia31546bac1327a3e0b5d37e8b99c808442d5e53f
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- 06 Jun, 2020 4 commits
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Alex Leibovich authored
Remove pll powerdown from pll configuration sequence to improve stability. Remove redundant cases, which no longer exist. Also get rid of irrelevant definition of CPU_2200_DDR_1200_RCLK_1200, which is not used by 806/807. Change-Id: If911e7dee003dfb9a42fafd7ffe34662f026fd23 Signed-off-by: Alex Leibovich <alexl@marvell.com>
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Grzegorz Jaszczyk authored
The mci_initialize function name was misleading. The function itself doesn't initialize MCI in general but performs MCI link tuning for performance improvement. Change-Id: I13094ad2235182a14984035bbe58013ebde84a7e Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Grzegorz Jaszczyk authored
By default all external CPs start with configuration address space set to 0xf200_0000. To overcome this issue, go in the loop and initialize the CP one by one, using temporary window configuration which allows to access each CP and update its configuration space according to decoding windows scheme defined for each platform. In case of cn9130 after this procedure bellow addresses will be used: CP0 - f2000000 CP1 - f4000000 CP2 - f6000000 When the re-configuration is done there is need to restore previous decoding window configuration(init_io_win). Change-Id: I1a652bfbd0bf7106930a7a4e949094dc9078a981 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Grzegorz Jaszczyk authored
Change-Id: Icb8fe14417665d6aadd5a5ee2b77547b4ef78773 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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- 03 Jun, 2020 1 commit
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Etienne Carriere authored
ETZPC stands for Extended TrustZone Protection Controller. It is a resource conditional access device. It is mainly based on Arm TZPC. ST ETZPC exposes memory mapped DECPROT cells to set access permissions to SoC peripheral interfaces as I2C, SPI, DDR controllers, and some of the SoC internal memories. ST ETZPC exposes memory mapped TZMA cells to set access permissions to some SoC internal memories. Change-Id: I47ce20ffcfb55306dab923153b71e1bcbe2a5570 Co-developed-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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- 01 Jun, 2020 1 commit
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Etienne Carriere authored
Changes stm32mp1 reset driver to API to add a timeout argument to stm32mp_reset_assert() and stm32mp_reset_deassert() and a return value. With a supplied timeout, the functions wait the target reset state is reached before returning. With a timeout of zero, the functions simply load target reset state in SoC interface and return without waiting. Helper functions stm32mp_reset_set() and stm32mp_reset_release() use a zero timeout and return without a return code. This change updates few stm32 drivers and plat/stm32mp1 blé_plat_setup.c accordingly without any functional change. functional change. Change-Id: Ia1a73a15125d3055fd8739c125b70bcb9562c27f Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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- 19 May, 2020 1 commit
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Manish V Badarkhe authored
CoT used for BL1 and BL2 are moved to tbbr_cot_bl1.c and tbbr_cot_bl2.c respectively. Common CoT used across BL1 and BL2 are moved to tbbr_cot_common.c. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I2252ac8a6960b3431bcaafdb3ea4fb2d01b79cf5
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- 11 May, 2020 1 commit
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Etienne Carriere authored
Oscillators, PLLs and some system clocks can be related straight to a parent clock. Prior this change were only oscillators and few clocks supported by this look up. This changes adds PLLs and other system clocks. This enables for flexible use of clock tree exploration when computing a clock frequency value. Change-Id: I15ec98023a7095e3120a6954de59a4799d92c66b Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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- 28 Apr, 2020 1 commit
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Andre Przywara authored
The device tree parsing code for the STM32 platform is using its own FDT helper functions, some of them being rather generic. In particular the existing fdt_read_uint32_array() implementation is now almost identical to the new generic code in fdt_wrappers.c, so we can remove the ST specific version and adjust the existing callers. Compared to the original ST implementation the new version takes a pointer to the DTB as the first argument, and also swaps the order of the number of cells and the pointer. Change-Id: Id06b0f1ba4db1ad1f733be40e82c34f46638551a Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 07 Apr, 2020 1 commit
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Alexei Fedorov authored
This patch adds support for GICv4 extension. New `GIC_ENABLE_V4_EXTN` option passed to gicv3.mk makefile was added, and enables GICv4 related changes when set to 1. This option defaults to 0. Change-Id: I30ebe1b7a98d3a54863900f37eda4589c707a288 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 06 Apr, 2020 1 commit
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Alexei Fedorov authored
This patch provides support for GICv3.1 extended PPI and SPI range. The option is enabled by setting to 1 and passing `GIC_EXT_INTID` build flag to gicv3.mk makefile. This option defaults to 0 with no extended range support. Change-Id: I7d09086fe22ea531c5df51a8a1efd8928458d394 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 03 Apr, 2020 6 commits
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Sheetal Tigadoli authored
Add SPI Nor flash support Change-Id: I0cde3fdb4dcad5bcaf445b3bb48e279332bd28af Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
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Sheetal Tigadoli authored
Add iproc spi driver Change-Id: I652efab1efd9c487974dae9cb9d98b9b8e3759c4 Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
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Sheetal Tigadoli authored
Add emmc driver for Broadcom platforms Change-Id: I126a6dfccd41062cb0b856f2c2fb1f724730b95e Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
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Sheetal Tigadoli authored
Change-Id: Icfef5b6923dc292e637001045a334c499d346fe9 Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
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Sheetal Tigadoli authored
Change-Id: I5daa3f2b4b9d85cb857547a588571a9aa8ad05c2 Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
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Sheetal Tigadoli authored
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com> Change-Id: Ic1a392a633b447935fa3a7528326c97845f5b1bc
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- 02 Apr, 2020 1 commit
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Sandrine Bailleux authored
The chain of trust array is now always accessed through a fconf getter. This gives us an ideal spot to check for out-of-bound accesses. Change-Id: Ic5ea20e43cf8ca959bb7f9b60de7c0839b390add Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 01 Apr, 2020 2 commits
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Gilad Ben-Yossef authored
Add Crypto 713 support as crypto module and NVM counter provider. As files under include/drivers/arm/cryptocell/713/ are copied verbatim from the CryptoCell SBROM lib project they are filtered from checkpatch coding style check. Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Change-Id: I7c361772f00ca7d96481f81ac6cbb2704467e52c
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Scott Branden authored
Add support to retrieve plat_toc_flags value from FIP header flags. plat_toc_flags is for platform specific use. It is stored in FIP header by fiptool using --plat-toc-flags option. Change-Id: Ibadd91b4f28e6503f4426e4efd404bbe512ad124 Signed-off-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
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- 23 Mar, 2020 1 commit
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Yann Gautier authored
Correct the following warning given by sparse tool: include/drivers/raw_nand.h:158:3: warning: symbol '__packed' was not declared. Should it be static? Change-Id: I03bd9a8aee5cdc5212ce5225be8033f1a6e92bd9 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 17 Mar, 2020 1 commit
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Andre Przywara authored
There is really no reason to use and pass around a struct when its only member is the (fixed) base address. Remove the struct and just use the base address on its own inside the GPIO driver. Then set the base address automatically. This simplifies GPIO setup for users, which now don't need to deal with zeroing a struct and setting the base address anymore. Change-Id: I3060f7859e3f8ef9a24cc8fb38307b5da943f127 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 10 Mar, 2020 1 commit
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Alexei Fedorov authored
This patch provides separation of GICD, GICR accessor functions and adds new macros for GICv3 registers access as a preparation for GICv3.1 and GICv4 support. NOTE: Platforms need to modify to include both 'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the single helper file previously. Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 06 Mar, 2020 2 commits
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Sumit Garg authored
TBBR spec advocates for optional encryption of firmwares (see optional requirement: R060_TBBR_FUNCTION). So add an IO abstaction layer to support firmware decryption that can be stacked above any underlying IO/ packaging layer like FIP etc. It aims to provide a framework to load any encrypted IO payload. Also, add plat_get_enc_key_info() to be implemented in a platform specific manner as handling of encryption key may vary from one platform to another. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I9892e0ddf00ebecb8981301dbfa41ea23e078b03
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Sumit Garg authored
Add framework for autheticated decryption of data. Currently this patch optionally imports mbedtls library as a backend if build option "DECRYPTION_SUPPORT = aes_gcm" is set to perform authenticated decryption using AES-GCM algorithm. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I2966f0e79033151012bf4ffc66f484cd949e7271
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- 25 Feb, 2020 9 commits
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location for the coreboot memory console. This removes the base member from the coreboot specific data structure, but keeps the struct console_cbmc_t and its size member. Change-Id: I7f1dffd41392ba3fe5c07090aea761a42313fb5b Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I7a23327394d142af4b293ea7ccd90b843c54587c Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I07a07677153d3671ced776671e4f107824d3df16 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
*All* UART drivers in TF-A are storing their base address as a uintptr_t pointer in the first location of the UART specific driver data. Since the base address is a pretty natural and generic data item, we should integrate this into the generic console_t structure. That will not only allow to remove a lot of seemingly UART specific data structures, but also enables to simplify runtime choices between different UARTs, since they can share the same pointer. This patch just adds the new member, the existing data structures will be handled on a per-UART base in follow-up patches. Change-Id: I59ce49471ccc8f3b870f2cfd8a72ebfd0cb14d12 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I9f8b55414ab7965e431e3e86d182eabd511f32a4 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: Iea6ca26ff4903c33f0fad27fec96fdbabd4e0a91 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I836e26ff1771abf21fd460d0ee40e90a452e9b43 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I89c3ab2ed85ab941d8b38ced48474feb4aaa8b7e Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 07 Feb, 2020 3 commits
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Aditya Angadi authored
On systems that have multiple platform components that can interpret the SCMI messages, there is a need to support multiple SCMI channels (one each to those platform components). Extend the existing SCMI interface that currently supports only a single SCMI channel to support multiple SCMI channels. Change-Id: Ice4062475b903aef3b5e5bc37df364c9778a62c5 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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Aditya Angadi authored
In order to allow the MHUv2 driver to be usable with multiple MHUv2 controllers, use the base address of the controller from the platform information instead of the MHUV2_BASE_ADDR macro. Change-Id: I4dbab87b929fb0568935e6c8b339ce67937f8cd1 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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Louis Mayencourt authored
Use the firmware configuration framework to store the io_policies information inside the configuration device tree instead of the static structure in the code base. The io_policies required by BL1 can't be inside the dtb, as this one is loaded by BL1, and only available at BL2. This change currently only applies to FVP platform. Change-Id: Ic9c1ac3931a4a136aa36f7f58f66d3764c1bfca1 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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- 30 Jan, 2020 1 commit
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Grzegorz Jaszczyk authored
In order to access MG SRAM, the amb bridge needs to be configured which is done in bl2 platform init. For MG CM3, the image is only loaded to its SRAM and the CM3 itself is left in reset. It is because the next stage bootloader (e.g. u-boot) will trigger action which will take it out of reset when needed. This can happen e.g. when appropriate device-tree setup (which has enabled 802.3 auto-neg) will be chosen. In other cases the MG CM3 should not be running. Change-Id: I816ea14e3a7174eace068ec44e3cc09998d0337e Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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