- 24 Sep, 2020 1 commit
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Lionel Debieve authored
While restarting a new hash computation, STR register is not cleared. It needs to be written before each computation. Change-Id: If65902dd21f9c139ec5da3ca87721232f73710db Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 08 Jul, 2020 1 commit
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Etienne Carriere authored
Register in the shared resources driver the secure or non-secure state of the HASH instances. Note that only BL32 needs to register the shared peripheral because BL2 does not embed the shared resources driver. Change-Id: I7f78fa8e47da71d48ef8b1dfe4d6f040fe918d8b Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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- 01 Jun, 2020 1 commit
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Etienne Carriere authored
Changes stm32mp1 reset driver to API to add a timeout argument to stm32mp_reset_assert() and stm32mp_reset_deassert() and a return value. With a supplied timeout, the functions wait the target reset state is reached before returning. With a timeout of zero, the functions simply load target reset state in SoC interface and return without waiting. Helper functions stm32mp_reset_set() and stm32mp_reset_release() use a zero timeout and return without a return code. This change updates few stm32 drivers and plat/stm32mp1 blé_plat_setup.c accordingly without any functional change. functional change. Change-Id: Ia1a73a15125d3055fd8739c125b70bcb9562c27f Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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- 20 Sep, 2019 1 commit
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Lionel Debieve authored
The driver manages the HASH processor IP on STM32MP1 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I3b67c80c16d819f86b951dae29a6c465e51ad585
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