- 24 Sep, 2020 2 commits
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Yann Gautier authored
The call to fdt_get_status(node) has to be done after the DT is found to be valid. Fixes: 1fc2130c stm32mp1: update device tree and gpio functions Change-Id: I70f803aae3dde128a9e740f54c8837b64cb1a244 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Lionel Debieve authored
While restarting a new hash computation, STR register is not cleared. It needs to be written before each computation. Change-Id: If65902dd21f9c139ec5da3ca87721232f73710db Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 08 Jul, 2020 5 commits
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Etienne Carriere authored
Register in the shared resources driver the secure or non-secure state of the HASH instances. Note that only BL32 needs to register the shared peripheral because BL2 does not embed the shared resources driver. Change-Id: I7f78fa8e47da71d48ef8b1dfe4d6f040fe918d8b Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
Register in the shared resources driver the secure or non-secure state of the GPIO pins. Change-Id: Ifda473bcbbb0af799be6587961d6641edf887605 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
Register in the shared resources driver the secure or non-secure state of the IWDG instances. Change-Id: I3a3bc9525447f6a2a465891ca3a3fd5fe664ca07 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
Register in the shared resources driver the secure or non-secure state of the PMIC. Change-Id: Ic1f172ba62785018f8e9bb321782d725e2d2f434 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
Introduce stm32mp1_register_clock_parents_secure() in stm32mp1 clock driver to allow platform shared resources to register as secure the parent clocks of a clock registered as secure. Change-Id: I53a9ab6aa78ee840ededce67e7b12a84e08ee843 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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- 17 Jun, 2020 4 commits
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Etienne Carriere authored
This change implements SCMI channels for reading a SCMI message from a shared memory and call the SCMI message drivers to route the message to the target platform services. SMT refers to the shared memory management protocol which is used to get/put message/response in shared memory. SMT is a 28byte header stating shared memory state and exchanged protocol data. The processing entry for a SCMI message can be a secure interrupt or fastcall SMCCC invocation. SMT description in this implementation is based on the OP-TEE project [1] itself based in the SCP-firmware implementation [2]. Link: [1] https://github.com/OP-TEE/optee_os/commit/a58c4d706d2333d2b21a3eba7e2ec0cb257bca1d Link: [2] https://github.com/ARM-software/SCP-firmware.git Change-Id: I416c7dab5c67954c6fe80bae8d8cdfdcda66873e Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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Etienne Carriere authored
Adds SCMI reset domain protocol support in the SCMI message drivers as defined in SCMI specification v2.0 [1]. Not all the messages defined in the specification are supported. scmi_msg_get_rd_handler() sanitizes the message_id value against any speculative use of reset domain ID as a index since by SCMI specification, IDs are indices. This implementation is based on the OP-TEE project implementation [2] itself based on the SCP-firmware implementation [3] of the SCMI protocol server side. Link: [1] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf Link: [2] https://github.com/OP-TEE/optee_os/commit/56a1f10ed99d683ee3a8af29b6147a59a99ef3e0 Link: [3] https://github.com/ARM-software/SCP-firmware.git Change-Id: If7cf13de40a815dedb40dcd5af8b6bb6725d9078 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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Etienne Carriere authored
Adds SCMI clock protocol support in the SCMI message drivers as defined in SCMI specification v2.0 [1] for clock protocol messages. Platform can provide one of the plat_scmi_clock_*() handler for the supported operations set/get state/rate and others. scmi_msg_get_clock_handler() sanitizes the message_id value against any speculative use of clock ID as a index since by SCMI specification, IDs are indices. This implementation is based on the OP-TEE project implementation [2] itself based on the SCP-firmware implementation [3] of the SCMI protocol server side. Link: [1] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf Link: [2] https://github.com/OP-TEE/optee_os/commit/a7a9e3ba71dd908aafdc4c5ed9b29b15faa9692d Link: [3] https://github.com/ARM-software/SCP-firmware.git Change-Id: Ib56e096512042d4f7b9563d1e4181554eb8ed02c Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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Etienne Carriere authored
This change introduces drivers to allow a platform to create a basic SCMI service and register handlers for client request (SCMI agent) on system resources. This is the first piece of the drivers: an entry function, the SCMI base protocol support and helpers for create the response message. With this change, scmi_process_message() is the entry function to process an incoming SCMI message. The function expect the message is already copied from shared memory into secure memory. The message structure stores message reference and output buffer reference where response message shall be stored. scmi_process_message() calls the SCMI protocol driver according to the protocol ID in the message. The SCMI protocol driver will call defined platform handlers according to the message content. This change introduces only the SCMI base protocol as defined in SCMI specification v2.0 [1]. Not all the messages defined in the specification are supported. The SCMI message implementation is derived from the OP-TEE project [2] itself based on the SCP-firmware implementation [3] of the SCMI protocol server side. Link: [1] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf Link: [2] https://github.com/OP-TEE/optee_os/commit/ae8c8068098d291e6e55744dbc237ec39fd9840a Link: [3] https://github.com/ARM-software/SCP-firmware/tree/v2.6.0 Change-Id: I639c4154a39fca60606264baf8d32452641f45e9 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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- 03 Jun, 2020 1 commit
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Etienne Carriere authored
ETZPC stands for Extended TrustZone Protection Controller. It is a resource conditional access device. It is mainly based on Arm TZPC. ST ETZPC exposes memory mapped DECPROT cells to set access permissions to SoC peripheral interfaces as I2C, SPI, DDR controllers, and some of the SoC internal memories. ST ETZPC exposes memory mapped TZMA cells to set access permissions to some SoC internal memories. Change-Id: I47ce20ffcfb55306dab923153b71e1bcbe2a5570 Co-developed-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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- 01 Jun, 2020 1 commit
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Etienne Carriere authored
Changes stm32mp1 reset driver to API to add a timeout argument to stm32mp_reset_assert() and stm32mp_reset_deassert() and a return value. With a supplied timeout, the functions wait the target reset state is reached before returning. With a timeout of zero, the functions simply load target reset state in SoC interface and return without waiting. Helper functions stm32mp_reset_set() and stm32mp_reset_release() use a zero timeout and return without a return code. This change updates few stm32 drivers and plat/stm32mp1 blé_plat_setup.c accordingly without any functional change. functional change. Change-Id: Ia1a73a15125d3055fd8739c125b70bcb9562c27f Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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- 11 May, 2020 6 commits
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Etienne Carriere authored
Adds missing terminal new line character '\n' to debug traces, fix format as index is an unsigned value and use present tense rather than past tense in the printed message. Change-Id: I88c06ef4d3a11d97ff8e96875a3dd0f58a3c98b6 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
Enable few system clocks at related BL initialization. Change-Id: I12b35e8cdc128b993de4a1dc4c6e9d52624dd8d9 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
Oscillators and PLLs are not gated on stm32mp_clk_enable/disable() calls. This change prevents functions to panic when called for such always-on clocks. Gating these clocks is out of the scope of this change. Change-Id: Ie730553dea480b529de942446176db9119587832 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
Adds RTC clock to the list of the supported clocks. This allows stm32mp_clk_*() API functions to enable, disable and set and get rate for the clock RTC clock. Change-Id: I8efc3f00b1f22d1912f59d1846994e9e646d6614 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
The current implementation optimizes memory consumed by gateable clock table by storing bit mask and bit shift with 1 byte each. The issue is that register selector bit masks above the 7th LSBit cannot be stored. This change uses the shift info to shift the mask before it is used, allowing clock selector register bit fields to be spread on the 32 bits of the register as long as the mask fits in 8 contiguous bit at most. This change is needed to add the RTC clock to the gateable clocks table. Change-Id: I8a0fbcbf20ea383fb3d712f5064d2d307e44465d Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
Oscillators, PLLs and some system clocks can be related straight to a parent clock. Prior this change were only oscillators and few clocks supported by this look up. This changes adds PLLs and other system clocks. This enables for flexible use of clock tree exploration when computing a clock frequency value. Change-Id: I15ec98023a7095e3120a6954de59a4799d92c66b Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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- 05 May, 2020 1 commit
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Andre Przywara authored
The STM32 platform port parse DT nodes to find base address to peripherals. It does this by using its own implementation, even though this functionality is generic and actually widely useful outside of the STM32 code. Re-implement fdt_get_reg_props_by_name() on top of the newly introduced fdt_get_reg_props_by_index() function, and move it to fdt_wrapper.c. This is removes the assumption that #address-cells and #size-cells are always one. Change-Id: I6d584930262c732b6e0356d98aea50b2654f789d Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 29 Apr, 2020 1 commit
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Andre Przywara authored
The STM32 platform code uses its own set of FDT helper functions, although some of them are fairly generic. Remove the implementation of fdt_read_uint32_default() and implement it on top of the newly introduced fdt_read_uint32() function, then convert all users over. This also fixes two callers, which were slightly abusing the "default" semantic. Change-Id: I570533362b4846e58dd797a92347de3e0e5abb75 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 28 Apr, 2020 1 commit
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Andre Przywara authored
The device tree parsing code for the STM32 platform is using its own FDT helper functions, some of them being rather generic. In particular the existing fdt_read_uint32_array() implementation is now almost identical to the new generic code in fdt_wrappers.c, so we can remove the ST specific version and adjust the existing callers. Compared to the original ST implementation the new version takes a pointer to the DTB as the first argument, and also swaps the order of the number of cells and the pointer. Change-Id: Id06b0f1ba4db1ad1f733be40e82c34f46638551a Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 26 Mar, 2020 1 commit
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Yann Gautier authored
A speculative accesses to DDR could be done whereas it was not reachable and could lead to bus stall. To correct this the dynamic mapping in MMU is used. A first mapping is done for DDR tests with MT_NON_CACHEABLE attribute, once DDR access is setup. It is then unmapped and a new mapping DDR is done with cacheable attribute (through MT_MEMORY) to speed-up BL33 (or OP-TEE) load. The disabling of cache during DDR tests is also removed, as now useless. A call to new functions stm32mp_{,un}map_ddr_non_cacheable() is done instead. PLAT_XLAT_TABLES_DYNAMIC is activated globally as used in BL2 and BL32. BL33 max size is also updated to take into account the secure and shared memory areas. Those are used in OP-TEE case. Change-Id: I22c48b4a48255ee264991c34ecbb15bfe87e67c3 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 23 Mar, 2020 3 commits
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Yann Gautier authored
This issue was found with cppcheck in our downstream code: [drivers/st/io/io_stm32image.c:234] -> [drivers/st/io/io_stm32image.c:244]: (warning) Either the condition 'buffer!=0U' is redundant or there is possible null pointer dereference: local_buffer. Change-Id: Ieb615b7e485dc93bbeeed4cd8bf845eb84c14ac9 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
The variable is wrongly set to 0L, whereas it is an unsigned int, it should then be 0U. Change-Id: I0b164c0ea598ec8a503f1693da2f3789f59da238 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
Sparse issue: drivers/st/spi/stm32_qspi.c:445:5: warning: symbol 'stm32_qspi_init' was not declared. Should it be static? Cppcheck issue: [drivers/st/spi/stm32_qspi.c:175] -> [drivers/st/spi/stm32_qspi.c:187]: (style) Variable 'len' is reassigned a value before the old one has been used. [drivers/st/spi/stm32_qspi.c:178]: (style) The scope of the variable 'timeout' can be reduced. Change-Id: I575fb50766355a6717cbd193fc4a80ff1923014c Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 25 Feb, 2020 1 commit
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: Iea6ca26ff4903c33f0fad27fec96fdbabd4e0a91 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 20 Jan, 2020 2 commits
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Lionel Debieve authored
Add QSPI support (limited to read interface). Implements the memory map and indirect modes. Low level driver based on SPI-MEM operations. Change-Id: Ied698e6de3c17d977f8b497c81f2e4a0a27c0961 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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Lionel Debieve authored
Add fmc2_nand driver support. The driver implements only read interface for NAND devices. Change-Id: I3cd037e8ff645ce0d217092b96f33ef41cb7a522 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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- 10 Jan, 2020 1 commit
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Yann Gautier authored
IO seek offset can be set to values above UINT32_MAX, this change changes the seek offset argument from 'ssize_t' to 'signed long long'. Fixing platform seek functions to match the new interface update. Change-Id: I25de83b3b7abe5f52a7b0fee36f71e60cac9cfcb Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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- 03 Oct, 2019 1 commit
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Nicolas Le Bayon authored
Change-Id: I84f8a99be2dcdf7c51fbecdb324df8e2f32cc855 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 23 Sep, 2019 1 commit
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Lionel Debieve authored
This commit adds authentication binary support for STM32MP1. It prints the bootrom authentication result if signed image is used and authenticates the next loaded STM32 images. It also enables the dynamic translation table support (PLAT_XLAT_TABLES_DYNAMIC) to use bootrom services. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: Iba706519e0dc6b6fae1f3dd498383351f0f75f51
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- 20 Sep, 2019 2 commits
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Lionel Debieve authored
This BSEC service is a platform specific service. Implementation moved to the platform part. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I1f70ed48a446860498ed111acce01187568538c9
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Lionel Debieve authored
The driver manages the HASH processor IP on STM32MP1 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I3b67c80c16d819f86b951dae29a6c465e51ad585
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- 10 Sep, 2019 1 commit
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Yann Gautier authored
The STM32 console driver was pre-pending '\r' before '\n'. It is now managed by the framework with the flag: CONSOLE_FLAG_TRANSLATE_CRLF. Remove the code in driver, and add the flag for STM32MP1. Change-Id: I5d0d5d5c4abee0b7dc11c2f8707b1b5cf10149ab Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 02 Sep, 2019 5 commits
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Yann Gautier authored
DBLOCKSIZE should be filled such as the data size is 2^DBLOCKSIZE. Hence it is calculated with __builtin_ctz. Change-Id: Id6b5ff9b594afc4fc523a388011beed307e6abd1 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
If the max-frequency property is provided in the device tree mmc node, it should be managed. The max allowed frequency will be the min between this property value and what the card can support. Change-Id: I885b676c3300d2670a0fe4c6ecab87758b5893ad Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
This function can be used on several stm32mp devices, it is then moved in plat/st/common/stm32mp_common.c. Change-Id: I862debe39604410f71a9ddc28713026362e9ecda Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
This change enables LpDDR3 initialization with PMIC. Change-Id: I2409a808335dfacd69a8517cb8510cee98bb8161 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
To use spinlocks, MMU should be enabled, as well as data cache. A common function is created (moved from clock file). It is then used whenever a spinlock has to be taken, in BSEC and clock drivers. Change-Id: I94baed0114a2061ad71bd5287a91bf7f1c6821f6 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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