1. 17 Jan, 2019 1 commit
    • Anson Huang's avatar
      Support for NXP's i.MX8 SoCs timer IPC · 1552df5d
      Anson Huang authored
      
      
      NXP's i.MX8 SoCs have system controller (M4 core) which takes
      control of timer management, including watchdog, srtc and system
      counter etc., other clusters like Cortex-A35 can send out command
      via MU (Message Unit) to system controller for timer operation.
      
      This patch adds timer IPC(inter-processor communication) support.
      Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
      1552df5d
  2. 19 Jun, 2018 1 commit
    • Anson Huang's avatar
      Support for NXP's i.MX8 SoCs IPC · ff2743e5
      Anson Huang authored
      
      
      NXP's i.MX8 SoCs have system controller (M4 core)
      which takes control of clock management, power management,
      partition management, PAD management etc., other
      clusters like Cortex-A35 can send out command via MU
      (Message Unit) to system controller for clock/power
      management etc..
      
      This patch adds basic IPC(inter-processor communication) support.
      Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
      ff2743e5