- 01 Feb, 2019 1 commit
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Sandrine Bailleux authored
PLAT_ARM_NS_IMAGE_OFFSET is in fact not an offset relative to some base address, it is an absolute address. Rename it to avoid any confusion. Change-Id: I1f7f5e8553cb267786afe7e5f3cd4d665b610d3f Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 30 Jan, 2019 2 commits
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Antonio Nino Diaz authored
This reverts commit 2f370465 ("Add support for the SMC Calling Convention 2.0"). SMCCC v2.0 is no longer required for SPM, and won't be needed in the future. Removing it makes the SMC handling code less complicated. The SPM implementation based on SPCI and SPRT was using it, but it has been adapted to SMCCC v1.0. Change-Id: I36795b91857b2b9c00437cfbfed04b3c1627f578 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Sathees Balya authored
ARMv8.4-TTST (Small Translation tables) relaxes the lower limit on the size of translation tables by increasing the maximum permitted value of the T1SZ and T0SZ fields in TCR_EL1, TCR_EL2, TCR_EL3, VTCR_EL2 and VSTCR_EL2. This feature is supported in AArch64 state only. This patch adds support for this feature to both versions of the translation tables library. It also removes the static build time checks for virtual address space size checks to runtime assertions. Change-Id: I4e8cebc197ec1c2092dc7d307486616786e6c093 Signed-off-by: Sathees Balya <sathees.balya@arm.com>
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- 25 Jan, 2019 8 commits
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Ying-Chun Liu (PaulLiu) authored
This commit adds GPIO driver for RaspberryPi3. The GPIO driver for RPi3 also provides the way to do pinmux selections. Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
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Antonio Nino Diaz authored
Change-Id: I670ea80e0331c2d4b2ccfa563a45469a43f6902d Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: Ia601d5ad65ab199e747fb60af4979b7db477d249 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: Ida5dae39478654405d0ee31a6cbddb4579e76a7f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: Icc59cdaf2b56f6936e9847f1894594c671db2e94 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: I656753a1825ea7340a3708b950fa6b57455e9056 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: I8989d2aa0258bf3b50a856c5b81532d578600124 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Use full include paths like it is done for common includes. This cleanup was started in commit d40e0e08283a ("Sanitise includes across codebase"), but it only cleaned common files and drivers. This patch does the same to Arm platforms. Change-Id: If982e6450bbe84dceb56d464e282bcf5d6d9ab9b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 23 Jan, 2019 2 commits
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Varun Wadekar authored
This patch provides helper function to read the ID_AFR0_EL1 system register for platforms. Change-Id: Id5491b18e3bf9f619d98d6cc8efd9d2cf5918c9d Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Sathees Balya authored
On ARM platforms, the BL2 memory can be overlaid by BL31/BL32. The memory descriptors describing the list of executable images are created in BL2 R/W memory, which could be possibly corrupted later on by BL31/BL32 due to overlay. This patch creates a reserved location in SRAM for these descriptors and are copied over by BL2 before handing over to next BL image. Also this patch increases the PLAT_ARM_MAX_BL2_SIZE for juno when TBBR is enabled. Fixes ARM-Software/tf-issues#626 Change-Id: I755735706fa702024b4032f51ed4895b3687377f Signed-off-by: Sathees Balya <sathees.balya@arm.com>
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- 22 Jan, 2019 2 commits
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Andrew F. Davis authored
Valid addresses for GICR base are always a set calculable distance from the GICD and is based on the number of cores a given instance of GICv3 IP can support. The formula for the number of address bits is given by the ARM GIC-500 TRM section 3.2 as 2^(18+log2(cores)) with the MSB set to one for GICR instances. Holes in the GIC address space are also guaranteed to safely return 0 on reads. This allows us to support runtime detection of the GICR base address by starting from GIC base address plus BIT(18) and walking until the GICR ID register (IIDR) is detected. We stop searching after BIT(20) to prevent searching out into space if something goes wrong. This can be extended out if we ever have a device with 16 or more cores. Signed-off-by: Andrew F. Davis <afd@ti.com>
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Antonio Nino Diaz authored
The SPM implementation based on MM is going to be kept for the foreseeable future. Change-Id: I11e96778a4f52a1aa803e7e048d9a7cb24a53954 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Acked-by: Sumit Garg <sumit.garg@linaro.org>
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- 18 Jan, 2019 6 commits
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Yann Gautier authored
The BSEC (Boot and Security and OTP control) is intended to control an OTP (one time programmable) fuse box, used for on-chip non-volatile storage for device configuration and security parameters. Change-Id: I38c44684c7b9c6a1f24ec0ae3fe99cec481d5a51 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
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Yann Gautier authored
Change fdt_check_status function to fdt_get_status. Update GPIO defines. Move some functions in gpio driver, instead of dt helper file. Add GPIO bank helper functions. Use only one status field in dt_node_info structure including both status and secure status. Change-Id: I34f93408dd4aac16ae722f564bc3f7d6ae978cf4 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
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Yann Gautier authored
Reword some traces. Use uintptr_t where required. Reduce scope of variables. Improve io_stm32image algo. Complete some IP registers definitions. Add failure on supported DDR (stm32mp1_ddr_init()). Fix cache flush on cache disable (stm32mp1_ddr_setup). Change-Id: Ie02fa71e02b9d69abc807fd5b7df233e5be6668c Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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Yann Gautier authored
Change-Id: I4a1b281925e0a3a1e2a34b3e363537e4a7f13823 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
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Yann Gautier authored
The drivers are also updated to reflect the changes. Set RCC as non-secure. Change-Id: I568fa1f418355830ad1d4d1cdcdb910fb362231b Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
This is the correct name of the IP. Rename stm32mp1_pmic files to stm32mp_pmic. Change-Id: I238a7d1f9a1d099daf7788dc9ebbd3146ba2f15f Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 15 Jan, 2019 2 commits
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Antonio Nino Diaz authored
From now on, platform_def.h must include any header with definitions that are platform-specific (like arm_def.h) and the included headers mustn't include back platform_def.h, and shouldn't be used by other files. Only platform_def.h should be included in other files. This will ensure that all needed definitions are present, rather than needing to include all the headers in all the definitions' headers just in case. This also prevents problems like cyclic dependencies. Change-Id: I9d3cf4d1de4b956fa035c79545222697acdaf5ca Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
The definitions in bl1/bl1_private.h and bl2/bl2_private.h are useful for platforms that may need to access them. Change-Id: Ifd1880f855ddafcb3bfcaf1ed4a4e0f121eda174 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 11 Jan, 2019 1 commit
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Antonio Nino Diaz authored
ARMv8.2-TTCNP is mandatory from ARMv8.2 onwards, but it can be implemented in CPUs that don't implement all mandatory 8.2 features (and so have to claim to be a lower version). This patch removes usage of the ARM_ARCH_AT_LEAST() macro and uses system ID registers to detect whether it is needed to set the bit or not. Change-Id: I7bcbf0c7c937590dfc2ca668cfd9267c50f7d52c Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 08 Jan, 2019 1 commit
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Ard Biesheuvel authored
Update some asserts that refer to #defines that only occur in ARM platforms, preventing this code to be used on other platforms. Instead, use a platform agnostic name, and update all the existing users. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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- 07 Jan, 2019 2 commits
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Soby Mathew authored
The patch SHA 55cf015c enabled PIE support when RESET_TO_BL31=1 for all ARM platforms. But it seems n1sdp platform doesn't work with PIE support yet. Hence restrict the ENABLE_PIE=1 to fvp platform. Change-Id: If44e42528e4b0b57c69084503f346576fe0748bd Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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Yann Gautier authored
Instead, only platform_def.h is included. The required files to be included are added in stm32mp1_def.h. Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 04 Jan, 2019 3 commits
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
The architecture dependant header files in include/lib/${ARCH} and include/common/${ARCH} have been moved to /include/arch/${ARCH}. Change-Id: I96f30fdb80b191a51448ddf11b1d4a0624c03394 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Even though this is not used unless SPD=tspd, only defining it when SPD_tspd is defined doesn't have any advantage and it makes it harder to read the code. Change-Id: I3d93135e05f39be071d16f8a47394a9a3ff54bc8 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 03 Jan, 2019 1 commit
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Sathees Balya authored
This patch enables the Data Independent Timing functionality (DIT) in EL3 if supported by the platform. Change-Id: Ia527d6aa2ee88a9a9fe1c941220404b9ff5567e5 Signed-off-by: Sathees Balya <sathees.balya@arm.com>
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- 18 Dec, 2018 3 commits
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Antonio Nino Diaz authored
This is done in order to keep the files in both repositories in sync. Change-Id: Ie1a9f321cbcfe8d7d14f206883fa718872271218 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: I8a0be21783a0c12325e6ab22e9e53ab5466ed9e0 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Some of the affected macros can only be used from C code. In general, we use arch_helpers.h for any C helpers to access registers. For consistency, the other macros have been moved as well. Also, import some AArch32 helpers from TF-A-Tests. Change-Id: Ie8fe1ddeadba5336c12971ddc39a7883121386b1 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 17 Dec, 2018 1 commit
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Soby Mathew authored
This patch defines BL31_BASE to 0x0 when RESET_TO_BL31=1 as the executable is built with PIE support and can be loaded anywhere in SRAM for execution. Change-Id: I4007f4626322f1200a6304c9c565987d3357986c Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 14 Dec, 2018 1 commit
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Jeenu Viswambharan authored
The GIC lowest priority values for each world depends on the number of priority values implemented in hardware. These constants currently defined in gic_common.h only meant to enumerate lowest possible architectural values. Since these values are not used in generic code or upstream platforms, and that general use of these constants can be wrong, remove these. Platforms should either define and use these as appropriate, or determine correct values at run time. Change-Id: I3805cea8ceb8a592b9eff681ea1b63b7496cec5f Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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- 11 Dec, 2018 4 commits
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Antonio Nino Diaz authored
Also, add a disclaimer to explain that the current implementation of SPM is a prototype that is going to undergo a lot of rework. Change-Id: I303c1e61c51d9f286cc599fea565fc9ba5a996bf Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
The old SMCs SP_MEMORY_ATTRIBUTES_{GET,SET}_AARCH64 have been removed in favour of SPRT_MEMORY_PERM_ATTR_{GET,SET}_AARCH64. Change-Id: Idb93cfa5461d0098df941037c5653f7c44b65227 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
This buffer is where all the responses from Secure Partitions are stored until they are requested. Change-Id: Iafeb8f0848c5ff6f3e187060cd3a47702484dc45 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: If57ec9cc0791f49d9ade83dff9d24ef9047963a8 Co-authored-by: Jean-Paul Etienne <jean-paul.etienne@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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