- 24 Jan, 2020 1 commit
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by:
Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I624c15d569db477506a74964bc828e1a932181d4
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- 20 Sep, 2019 2 commits
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Kever Yang authored
Rockchip platform is using the first 1MB of DRAM as secure ram space, and there is a vendor loader who loads and runs the BL31/BL32/BL33, this loader is usually load by SoC BootRom to the start addres of DRAM, we need to reserve enough space for this loader so that it doesn't need to do the relocate when loading the BL31. eg. We use U-Boot SPL to load ATF BL31 and U-Boot proper as BL33, the SPL TEXT BASE is offset 0 of DRAM which is decide by Bootrom; if we update the BL31_BASE to offset 0x40000(256KB), then the 0~0x40000 should be enough for SPL and no need to do the relocate while the space size 0x10000(64KB) may not enough for SPL. After this update, the BL31 can use the rest 768KB of the first 1MB, which is also enough, and the loader who is using BL31 elf file can support this update without any change. Change-Id: I66dc685594d77f10f9a49c3be015fd6729250ece Signed-off-by:
Kever Yang <kever.yang@rock-chips.com>
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Kever Yang authored
The 'txet' should be 'text'. Change-Id: I2217a1adf50c3b86f3087b83c77d9291b280627c Signed-off-by:
Kever Yang <kever.yang@rock-chips.com>
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- 01 May, 2019 1 commit
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Christoph Müllner authored
In order to set the UART base during bootup in common code of plat/rockchip, we need to streamline the way the UART base addresses are defined and add the missing definitions and mappings. This patch does so by following the pattern UARTn_BASE, which is already in use on RK3399 and RK3328. The numbering itself is derived from the upstream Linux DTS files of the individual SoCs. Signed-off-by:
Christoph Müllner <christophm30@gmail.com> Change-Id: I341a1996f4ceed5f82a2f6687d4dead9d7cc5c1f
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- 25 Apr, 2019 1 commit
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Heiko Stuebner authored
The rk3288 is a 4-core Cortex-A12 SoC and shares a lot of features with later SoCs. Working features are general non-secure mode (the gic needs special love for that), psci-based smp bringing cpu cores online and also taking them offline again, psci-based suspend (the simpler variant also included in the linux kernel, deeper suspend following later) and I was also already able to test HYP-mode and was able to boot a virtual kernel using kvm. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Change-Id: Ibaaa583b2e78197591a91d254339706fe732476a
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