- 29 Apr, 2021 1 commit
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Manish V Badarkhe authored
Added GPT parser support in BL2 for Arm platforms to get the entry address and length of the FIP in the GPT image. Also, increased BL2 maximum size for FVP platform to successfully compile ROM-enabled build with this change. Verified this change using a patch: https://review.trustedfirmware.org/c/ci/tf-a-ci-scripts/+/9654 Change-Id: Ie8026db054966653b739a82d9ba106d283f534d0 Signed-off-by:
Manish V Badarkhe <Manish.Badarkhe@arm.com>
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- 28 Apr, 2021 2 commits
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Manish V Badarkhe authored
Replaced PLAT_ARM_FIP_BASE and PLAT_ARM_FIP_MAX_SIZE macro with a generic name PLAT_ARM_FLASH_IMAGE_BASE and PLAT_ARM_FLASH_IMAGE_MAX_SIZE so that these macros can be reused in the subsequent GPT based support changes. Change-Id: I88fdbd53e1966578af4f1e8e9d5fef42c27b1173 Signed-off-by: -
Manish Pandey authored
* changes: fdts: stm32mp1: add support for the Seeed Odyssey SoM and board fdts: stm32mp1: add alternative SDMMC2 pins to the pinctrl fdts: stm32mp1: add I2C2 pins in the pinctrl fdts: stm32mp1: add the I2C2 peripheral in the SoC DTS
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- 27 Apr, 2021 6 commits
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Manish Pandey authored
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Pali Rohár authored
This new compile option is only for Armada 3720 Development Board. When it is set to 1 then TF-A will setup PM wake up src configuration. By default this new option is disabled as it is board specific and no other A37xx board has PM wake up src configuration. Currently neither upstream U-Boot nor upstream Linux kernel has wakeup support for A37xx platforms, so having it disabled does not cause any issue. Prior this commit PM wake up src configuration specific for Armada 3720 Development Board was enabled for every A37xx board. After this change it is enabled only when compiling with build flag A3720_DB_PM_WAKEUP_SRC=1 Signed-off-by:Pali Rohár <pali@kernel.org> Change-Id: I09fea1172c532df639acb3bb009cfde32d3c5766
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Manish Pandey authored
* changes: feat(board/rdn2): add support for variant 1 of rd-n2 platform feat(plat/sgi): introduce platform variant build option
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Aditya Angadi authored
Add board support for RD-N2 Cfg1 variant of RD-N2 platform. It is a variant of RD-N2 platform with a reduced interconnect mesh size (3x3) and core count (8-cores). Its platform variant id is 1. Change-Id: I34ad35c5a5c1e9b69a658fb92ed00e5bc5fe72f3 Signed-off-by:Aditya Angadi <aditya.angadi@arm.com>
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Aditya Angadi authored
A Neoverse reference design platform can have two or more variants that differ in core count, cluster count or other peripherals. To allow reuse of platform code across all the variants of a platform, introduce build option CSS_SGI_PLATFORM_VARIANT for Arm Neoverse reference design platforms. The range of allowed values for the build option is platform specific. The recommended range is an interval of non negative integers. An example usage of the build option is make PLAT=rdn2 CSS_SGI_PLATFORM_VARIANT=1 Change-Id: Iaae79c0b4d0dc700521bf6e9b4979339eafe0359 Signed-off-by: -
Manish Pandey authored
* changes: plat/qemu: add "max" cpu support Add support for QEMU "max" CPU
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- 26 Apr, 2021 5 commits
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Manish Pandey authored
* changes: build: deprecate Arm sgm775 FVP platform docs: introduce process for platform deprecation
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Manish Pandey authored
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Manish Pandey authored
* changes: mediatek: mt8195: add rtc power off sequence mediatek: mt8195: add power-off support mediatek: mt8195: Add reboot function for PSCI mediatek: mt8195: Add gpio driver mediatek: mt8195: Add SiP service mediatek: mt8195: Add CPU hotplug and MCDI support mediatek: mt8195: Add MCDI drivers mediatek: mt8195: Add SPMC driver mediatek: mt8195: Initialize delay_timer mediatek: mt8195: initialize systimer mediatek: mt8192: move timer driver to common folder mediatek: mt8195: add sys_cirq support mediatek: mt8195: initialize GIC Initialize platform for MediaTek MT8195
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Manish Pandey authored
This will help in keeping source file generic and conditional compilation can be contained in platform provided dt files. Signed-off-by:Manish Pandey <manish.pandey2@arm.com> Change-Id: I3c6e0a429073f0afb412b9ba521ce43f880b57fe
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Olivier Deprez authored
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- 23 Apr, 2021 16 commits
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Manish Pandey authored
sgm775 is an old platform and is no longer maintained by Arm and its fast model FVP_CSS_SGM-775 is no longer available for download. This platform is now superseded by Total Compute(tc) platforms. This platform is now deprecated but the source will be kept for cooling off period of 2 release cycle before removing it completely. Signed-off-by: -
Manish Pandey authored
Signed-off-by: -
Yidi Lin authored
mt8195 also uses mt6359p RTC. Revice mt8192 RTC and share the driver with mt8195. Change-Id: I20c73f6e0af67ef9d4c3d4e0ff373f93950e07db Signed-off-by:Yidi Lin <yidi.lin@mediatek.com>
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Yidi Lin authored
mt8195 also uses PMIC mt6359p. The only difference is the pwrap register definition. Change-Id: I9962263c46187d1344f14f857bf4b51e33aedda0 Signed-off-by: -
Yidi Lin authored
Add system_reset function in PSCI ops Signed-off-by: -
mtk20895 authored
Add gpio driver. Signed-off-by:mtk20895 <zhiqiang.ma@mediatek.com> Change-Id: I6ff6875c35294f56f2d8298d75cd18c230aad211
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Yidi Lin authored
Add the basic SiP service Change-Id: I21fe9d85eac4be9101b12c4b6c28294c5b93cb5f Signed-off-by: -
James Liao authored
Implement PSCI platform OPs to support CPU hotplug and MCDI. Signed-off-by:James Liao <jamesjj.liao@mediatek.com> Change-Id: I1321f7989c8a3d116d698768a7146e8f180ee9c0
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James Liao authored
Add MCDI related drivers to handle CPU powered on/off in CPU suspend. Signed-off-by: -
James Liao authored
Add SPMC driver for CPU power on/off. Signed-off-by: -
Yidi Lin authored
Initialize delay_timer for delay functions. Change-Id: Ib554135151f8b5c642b5a6511c942bb9efc0a47f Signed-off-by: -
Yidi Lin authored
Change-Id: I7e0fbd04b0cdf5da92b8ef39737342f2d66f5f10 Signed-off-by: -
Yidi Lin authored
The timer driver can be shared with mt8195. Move the the timer driver to common/. Signed-off-by: -
gtk_pangao authored
MT8192 cirq driver can be shared with MT8195. Move cirq driver to common common folder. Signed-off-by:gtk_pangao <gtk_pangao@mediatek.com> Change-Id: Iba5cdcfd2116f0bd07e0497250f2da45613e3a4f
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christine.zhu authored
MT8192 GIC driver can be shared with MT8195. Move GIC driver to common and do the initialization. Signed-off-by:christine.zhu <christine.zhu@mediatek.corp-partner.google.com> Change-Id: I63f3e668b5ca6df8bcf17b5cd4d53fa84f330fed
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Yidi Lin authored
- Add basic platform setup - Add MT8195 documentation at docs/plat/ - Add generic CPU helper functions - Add basic register address Change-Id: I7978e2f32e58900e5cf93f741ee8eaf8b8e3b842 Signed-off-by:
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- 22 Apr, 2021 7 commits
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Manish Pandey authored
* changes: plat/qemu: add cortex-a72 support to 'virt' platform plat/qemu: include gicv2.mk
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Manish Pandey authored
* changes: plat: send an sgi to communicate to linux plat: xilinx: Error management support
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Venkatesh Yadav Abbarapu authored
Upon recieving the interrupt send an SGI. The sgi number is communicated by linux. Signed-off-by:
Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Change-Id: Ib8f07ff7132ba5ac202b546914efb16d04820ed3 Signed-off-by:
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
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Shubhrajyoti Datta authored
Add support for the trapping the IPI in TF-A. Register handler for the irq no 62 which is the IPI interrupt. Signed-off-by:
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Manish Pandey authored
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Madhukar Pappireddy authored
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Manish Pandey authored
* changes: plat: imx8mm: Add in BL2 with FIP plat: imx8mm: Enable Trusted Boot
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- 21 Apr, 2021 3 commits
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Grzegorz Szymaszek authored
Seeed Studio’s SoM‐STM32MP157C is a System‐on‐Module that integrates the STM32MP157C MPU (the 650 MHz dual‐core variant with a GPU and a cryptographic processor) the STPMIC1A PMIC, 512 MB of DDR3 RAM and a 4 GB eMMC. There are two LEDs as well, one hardwired to the PMIC’s VDD output, and the other available at the MPU’s port PG3. The SoM can be plugged into a carrier board using its three 70‑pin connectors. Seeed Odyssey‐STM32MP157C is the reference carrier board for the SoM in a Raspberry Pi‐like form factor. It features a WiFi/Bluetooth chip, a microSD card port and various I/O interfaces. The device tree is based on the DKx boards. TF‑A was successfully tested on the board with Buildroot 2021.02 and U-Boot 2021.04. Signed-off-by:Grzegorz Szymaszek <gszymaszek@short.pl> Change-Id: I2c9aecc925561e8d338dddbb192d3bb23a533914
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Grzegorz Szymaszek authored
The new pins—PA8, PA9, PE5, and PC7—are described in a new pinctrl node named “sdmmc2-d47-3”, AKA phandle “sdmmc2_d47_pins_d”. These names are identical to their Linux kernel counterparts (commit 7af08140979a6e7e12b78c93b8625c8d25b084e2). Signed-off-by: -
Grzegorz Szymaszek authored
Some STM32MP1‐based boards, like Seeed Studio’s SoM‐STM32MP157C, have the SoC connected to the PMIC via I2C2 instead of I2C4 (which is used on the official ST development boards). This commit brings TF‑A one step closer to boot on such boards. The pins used, PH4 and PH5, are described in a new pinctrl node named “i2c2-0”, AKA phandle “i2c2_pins_a”. These names are identical to their Linux kernel counterparts (commit 7af08140979a6e7e12b78c93b8625c8d25b084e2). Signed-off-by:
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