- 30 Mar, 2017 1 commit
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Varun Wadekar authored
This patch adds a helper function to the MCE driver to allow its clients to issue UPDATE_CSTATE_INFO requests, without having to setup the CPU context struct. We introduced a struct to encapsulate the request parameters, that clients can pass on to the MCE driver. The MCE driver gets the parameters from the struct and programs the hardware accordingly. Change-Id: I02bce57506c4ccd90da82127805d6b564375cbf1 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 23 Mar, 2017 2 commits
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Varun Wadekar authored
This patch checks that the system is running with the supported MCE firmware during boot. In case the firmware version does not match the interface header version, then the system halts. Change-Id: Ib82013fd1c1668efd6f0e4f36cd3662d339ac076 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds a new interface to allow for making an ARI call that will enable LATIC for the chip verification software harness. LATIC allows some MINI ISMs to be read in the CCPLEX. The ISMs are used for various measurements relevant ot particular locations in Silicon. They are small counters which can be polled to determine how fast a particular location in the Silicon is. Original change by Guy Sotomayor <gsotomayor@nvidia.com> Change-Id: Ifb49b8863a009d4cdd5d1ba38a23b5374500a4b3 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 20 Mar, 2017 1 commit
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Varun Wadekar authored
The CPU Complex (CCPLEX) Power Manager (Denver MCE, or DMCE) is an offload engine for BPMP to do voltage related sequencing and for hardware requests to be handled in a better latency than BPMP-firmware. There are two interfaces to the MCEs - Abstract Request Interface (ARI) and the traditional NVGINDEX/NVGDATA interface. MCE supports various commands which can be used by CPUs - ARM as well as Denver, for power management and reset functionality. Since the linux kernel is the master for all these scenarios, each MCE command can be issued by a corresponding SMC. These SMCs have been moved to SiP SMC space as they are specific to the Tegra186 SoC. Change-Id: I67bee83d2289a8ab63bc5556e5744e5043803e51 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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