1. 08 Nov, 2018 1 commit
    • Antonio Nino Diaz's avatar
      Standardise header guards across codebase · c3cf06f1
      Antonio Nino Diaz authored
      
      
      All identifiers, regardless of use, that start with two underscores are
      reserved. This means they can't be used in header guards.
      
      The style that this project is now to use the full name of the file in
      capital letters followed by 'H'. For example, for a file called
      "uart_example.h", the header guard is UART_EXAMPLE_H.
      
      The exceptions are files that are imported from other projects:
      
      - CryptoCell driver
      - dt-bindings folders
      - zlib headers
      
      Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      c3cf06f1
  2. 18 Oct, 2018 1 commit
    • Grzegorz Jaszczyk's avatar
      mvebu: cp110: introduce COMPHY porting layer · 42a29337
      Grzegorz Jaszczyk authored
      
      
      Some of COMPHY parameters depends on the hw connection between the SoC
      and the PHY, which can vary on different boards e.g. due to different
      wires length. Define the "porting layer" with some defaults
      parameters. It ease updating static values which needs to be updated due
      to board differences, which are now grouped in one place.
      
      Example porting layer for a8k-db is under:
      plat/marvell/a8k/a80x0/board/phy-porting-layer.h
      
      If for some boards parameters are not defined (missing
      phy-porting-layer.h), the default values are used
      (drivers/marvell/comphy/phy-default-porting-layer.h)
      and the following compilation warning is show:
      "Using default comphy params - you may need to suit them to your board".
      
      The common COMPHY driver code is extracted in order to be shared with
      future COMPHY driver for A3700 SoC platforms
      Signed-off-by: default avatarGrzegorz Jaszczyk <jaz@semihalf.com>
      Signed-off-by: default avatarIgal Liberman <igall@marvell.com>
      Signed-off-by: default avatarKonstantin Porotchkin <kostap@marvell.com>
      42a29337
  3. 02 Sep, 2018 2 commits
    • Marcin Wojtas's avatar
      plat: marvell: a70x0: reconfigure CP0 PCIE2 windows · 5b0a152a
      Marcin Wojtas authored
      
      
      In order to allow the use of PCIe cards such as graphics cards, whose
      demands for BAR space are typically much higher than those of network
      or SATA/USB cards, reconfigure the I/O windows so we can declare two
      MMIO PCI regions: a 512 MB MMIO32 one at 0xc000_0000 and a 4 GB MMIO64
      one at 0x8_0000_0000. In addition, this will leave ample room for an
      ECAM config space at 0xe000_0000 (up to the ECAM maximum of 256 MB)
      
      For compatibility with older kernels or firmware, leave the original
      16 MB window in place as well.
      
      Change-Id: I80b00691ae8d0a3f3f7285b8e0bfc21c0a095e94
      Signed-off-by: default avatarMarcin Wojtas <mw@semihalf.com>
      Reviewed-by: default avatarKostya Porotchkin <kostap@marvell.com>
      5b0a152a
    • Konstantin Porotchkin's avatar
      plat: marvell: rename common include file · 94d6dd67
      Konstantin Porotchkin authored
      
      
      Rename a8k_common.h to armada_common.h to keep the same header
      name across all other Marvell Armada platforms.
      This is especially useful since various Marvell platforms may
      use common platform files and share the driver modules.
      
      Change-Id: I7262105201123d54ccddef9aad4097518f1e38ef
      Signed-off-by: default avatarKonstantin Porotchkin <kostap@marvell.com>
      94d6dd67
  4. 18 Jul, 2018 1 commit