Skip to content

GitLab

Switch branch/tag
  1. 02 Aug, 2018 2 commits
  3. 30 Jul, 2018 1 commit
  5. 26 Jul, 2018 2 commits
  7. 24 Jul, 2018 4 commits
  9. 20 Jul, 2018 3 commits
  11. 15 Jul, 2018 2 commits
  13. 13 Jul, 2018 4 commits
    • Antonio Nino Diaz's avatar
      xlat v2: Turn MMU parameters into 64-bit values · 6563c0be
      Antonio Nino Diaz authored 
      

Most registers are 64-bit wide, even in AArch32 mode:

- MAIR_ELx is equivalent to MAIR0 and MAIR1.
- TTBR is 64 bit in both AArch64 and AArch32.

The only difference is the TCR register, which is 32 bit in AArch32 and
in EL3 in AArch64. For consistency with the rest of ELs in AArch64, it
makes sense to also have it as a 64-bit value.

Change-Id: I2274d66a28876702e7085df5f8aad0e7ec139da9
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      6563c0be
    • Antonio Nino Diaz's avatar
      xlat v2: Remove IMAGE_EL define · aa1d5f60
      Antonio Nino Diaz authored 
      

The Exception Level is now detected at runtime. This means that it is not
needed to hardcode the EL used by each image.

This doesn't result in a substantial increase of the image size because
the initialization functions that aren't used are garbage-collected by
the linker.

In AArch32 the current EL has been changed from EL3 to EL1 because the
the AArch32 PL1&0 translation regime behaves more like the AArch64 EL1&0
translation regime than the EL3 one.

Change-Id: I941404299ebe7666ca17619207c923b49a55cb73
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      aa1d5f60
    • Antonio Nino Diaz's avatar
      xlat v2: Remove unused tlbi helper · 8d164bc6
      Antonio Nino Diaz authored 
      

xlat_arch_tlbi_va_regime() isn't used, so it has been renamed to
xlat_arch_tlbi_va() and the previous implementation has been removed.

Change-Id: Ic118bed3fb68234748d86b2e9e95b25650289276
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      8d164bc6
    • Antonio Nino Diaz's avatar
      xlat v2: Remove architectural headers · 468e2382
      Antonio Nino Diaz authored 
      

They only contained one function that is easily integrated in the private
library header and the existing architectural C files.

This also helps making the library more portable, as the Makefile of the
library now doesn't use the variable INCLUDES, which is specific to this
codebase and doesn't respect the namespace of the library.

Change-Id: I22228e6a97e9b4f346f5cd8947609263e8df71d8
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      468e2382
  15. 11 Jul, 2018 3 commits
  17. 10 Jul, 2018 1 commit
    • Roberto Vargas's avatar
      Fix MISRA rule 8.3 · c96f297f
      Roberto Vargas authored 
      

Rule 8.3: All declarations of an object or function shall
              use the same names and type qualifiers.

Fixed for:
	make DEBUG=1 PLAT=juno ARCH=aarch32 AARCH32_SP=sp_min RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32

Change-Id: Ia34f5155e1cdb67161191f69e8d1248cbaa39e1a
Signed-off-by: default avatarRoberto Vargas <roberto.vargas@arm.com>
      c96f297f
  19. 03 Jul, 2018 3 commits
    • Antonio Nino Diaz's avatar
      xlat v2: Make get/set attrs functions less verbose · 6a086061
      Antonio Nino Diaz authored 
      

It is useful to have LOG_LEVEL_VERBOSE because it prints the memory map
of each image, but that also means that the change_mem_attributes and
get_mem_attributes functions have verbose prints, and generate a too
long text output that hides other useful information.

As they were mostly there for debug purposes, this patch removes them.

Change-Id: I2986537377d1f78be2b79cc8a6cf230c380bdb55
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      6a086061
    • Antonio Nino Diaz's avatar
      xlat v2: Clean debug xlat tables descriptor print · f9d58d17
      Antonio Nino Diaz authored 
      

The previous debug output for EL1&0 translation regimes was too verbose,
which makes it hard to read and hides the intent behind the parameters
assigned to each region. This patch simplifies this output and makes the
outputs for EL3 and EL1&0 mostly the same. The difference is that in
EL1&0 it is specified whether the region is exclusively accessible from
EL1 (PRIV) or both EL0 and EL1 (USER).

For example:

    MEM-RW(PRIV)-NOACCESS(USER)-XN(PRIV)-XN(USER)-S
    MEM-RO(PRIV)-NOACCESS(USER)-EXEC(PRIV)-EXEC(USER)-S

After the change, it becomes this:

    MEM-RW-XN-PRIV-S
    MEM-RO-EXEC-PRIV-S

Change-Id: I15f4b99058429d42107fbf89e15f4838a9b559a5
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      f9d58d17
    • Antonio Nino Diaz's avatar
      xlat v2: Split code into separate files · fd2299e6
      Antonio Nino Diaz authored 
      

Instead of having one big file with all the code, it's better to have
a few smaller files that are more manageable:

- xlat_tables_core.c: Code related to the core functionality of the
  library (map and unmap regions, initialize xlat context).
- xlat_tables_context.c: Instantiation of the active image context
  as well as APIs to manipulate it.
- xlat_tables_utils.c: Helper code that isn't part of the core
  functionality (change attributes, debug print messages).

Change-Id: I3ea956fc1afd7473c0bb5e7c6aab3b2e5d88c711
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      fd2299e6
  21. 27 Jun, 2018 3 commits
    • Jeenu Viswambharan's avatar
      DynamIQ: Enable MMU without using stack · 64ee263e
      Jeenu Viswambharan authored 
      

Having an active stack while enabling MMU has shown coherency problems.
This patch builds on top of translation library changes that introduces
MMU-enabling without using stacks.

Previously, with HW_ASSISTED_COHERENCY, data caches were disabled while
enabling MMU only because of active stack. Now that we can enable MMU
without using stack, we can enable both MMU and data caches at the same
time.

NOTE: Since this feature depends on using translation table library v2,
disallow using translation table library v1 with HW_ASSISTED_COHERENCY.

Fixes ARM-software/tf-issues#566

Change-Id: Ie55aba0c23ee9c5109eb3454cb8fa45d74f8bbb2
Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      64ee263e
    • Jeenu Viswambharan's avatar
      xlat v1: Provide direct MMU-enabling stubs · 92bec97f
      Jeenu Viswambharan authored 
      

An earlier patch split MMU-enabling function for translation library v2.
Although we don't intend to introduce the exact same functionality for
xlat v1, this patch introduces stubs for directly enabling MMU to
maintain API-compatibility.

Change-Id: Id7d56e124c80af71de999fcda10f1734b50bca97
Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      92bec97f
    • Jeenu Viswambharan's avatar
      xlat v2: Split MMU setup and enable · 0cc7aa89
      Jeenu Viswambharan authored 
      

At present, the function provided by the translation library to enable
MMU constructs appropriate values for translation library, and programs
them to the right registers. The construction of initial values,
however, is only required once as both the primary and secondaries
program the same values.

Additionally, the MMU-enabling function is written in C, which means
there's an active stack at the time of enabling MMU. On some systems,
like Arm DynamIQ, having active stack while enabling MMU during warm
boot might lead to coherency problems.

This patch addresses both the above problems by:

  - Splitting the MMU-enabling function into two: one that sets up
    values to be programmed into the registers, and another one that
    takes the pre-computed values and writes to the appropriate
    registers. With this, the primary effectively calls both functions
    to have the MMU enabled, but secondaries only need to call the
    latter.

  - Rewriting the function that enables MMU in assembly so that it
    doesn't use stack.

This patch fixes a bunch of MISRA issues on the way.

Change-Id: I0faca97263a970ffe765f0e731a1417e43fbfc45
Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      0cc7aa89
  23. 22 Jun, 2018 1 commit
    • Antonio Nino Diaz's avatar
      xlat: Remove mmap_attr_t enum type · 3a1b7b10
      Antonio Nino Diaz authored 
      

The values defined in this type are used in logical operations, which
goes against MISRA Rule 10.1: "Operands shall not be of an inappropriate
essential type".

Now, `unsigned int` is used instead. This also allows us to move the
dynamic mapping bit from 30 to 31. It was an undefined behaviour in the
past because an enum is signed by default, and bit 31 corresponds to the
sign bit. It is undefined behaviour to modify the sign bit. Now, bit 31
is free to use as it was originally meant to be.

mmap_attr_t is now defined as an `unsigned int` for backwards
compatibility.

Change-Id: I6b31218c14b9c7fdabebe432de7fae6e90a97f34
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      3a1b7b10
  25. 21 Jun, 2018 2 commits
  27. 19 Jun, 2018 1 commit
  29. 14 Jun, 2018 1 commit
    • Yann Gautier's avatar
      xlat_v2: add a check on mm_cursor->size to avoid infinite loop · 75df6269
      Yann Gautier authored 
      

The issue can occur if end_va is equal to the max architecture address,
and when mm_cursor point to the last entry of mmap_region_t table: {0}.
The first line of the while will then be true, e.g. on AARCH32, we have:
mm_cursor->base_va (=0) + mm_cursor->size (=0) - 1 == end_va (=0xFFFFFFFF)
And the mm_cursor->size = 0 will be lesser than mm->size

A check on mm_cursor->size != 0 should be done as in the previous while,
to avoid such kind of infinite loop.

fixes arm-software/tf-issues#594
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      75df6269
  31. 13 Jun, 2018 1 commit
    • Antonio Nino Diaz's avatar
      xlat v2: Introduce xlat granule size helpers · a0b9bb79
      Antonio Nino Diaz authored 
      

The function xlat_arch_is_granule_size_supported() can be used to check
if a specific granule size is supported. In Armv8, AArch32 only supports
4 KiB pages. AArch64 supports 4 KiB, 16 KiB or 64 KiB depending on the
implementation, which is detected at runtime.

The function xlat_arch_get_max_supported_granule_size() returns the max
granule size supported by the implementation.

Even though right now they are only used by SPM, they may be useful in
other places in the future. This patch moves the code currently in SPM
to the xlat tables lib so that it can be reused.

Change-Id: If54624a5ecf20b9b9b7f38861b56383a03bbc8a4
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      a0b9bb79
  33. 12 Jun, 2018 4 commits
    • Daniel Boulby's avatar
      Fix MISRA Rule 5.7 Part 3 · 776ff52a
      Daniel Boulby authored 
      

Rule 5.7: A tag name shall be a unique identifier

Follow convention of shorter names for smaller scope to fix
violations of MISRA rule 5.7

Fixed For:
    make ARM_TSP_RAM_LOCATION=tdram LOG_LEVEL=50 PLAT=fvp SPD=opteed

Change-Id: I5fbb5d6ebddf169550eddb07ed880f5c8076bb76
Signed-off-by: default avatarDaniel Boulby <daniel.boulby@arm.com>
      776ff52a
    • Daniel Boulby's avatar
      Fix MISRA Rule 5.7 Part 1 · 40692923
      Daniel Boulby authored 
      

Rule 5.7: A tag name shall be a unique identifier

There were 2 amu_ctx struct type definitions:
    - In lib/extensions/amu/aarch64/amu.c
    - In lib/cpus/aarch64/cpuamu.c

Renamed the latter to cpuamu_ctx to avoid this name clash

To avoid violation of Rule 8.3 also change name of function
amu_ctxs to unique name (cpuamu_ctxs) since it now returns a
different type (cpuamu_ctx) than the other amu_ctxs function

Fixed for:
    make LOG_LEVEL=50 PLAT=fvp

Change-Id: Ieeb7e390ec2900fd8b775bef312eda93804a43ed
Signed-off-by: default avatarDaniel Boulby <daniel.boulby@arm.com>
      40692923
    • Daniel Boulby's avatar
      Fix MISRA Rule 5.3 Part 4 · 7cb81945
      Daniel Boulby authored 
      

Use a _ prefix for macro arguments to prevent that argument from
hiding variables of the same name in the outer scope

Rule 5.3: An identifier declared in an inner scope shall not
          hide an identifier declared in an outer scope

Fixed For:
    make PLAT=fvp USE_COHERENT_MEM=0

Change-Id: If50c583d3b63799ee6852626b15be00c0f6b10a0
Signed-off-by: default avatarDaniel Boulby <daniel.boulby@arm.com>
      7cb81945
    • Daniel Boulby's avatar
      Fix MISRA Rule 5.3 Part 2 · 896a5902
      Daniel Boulby authored 
      

Use a _ prefix for Macro arguments to prevent that argument from
hiding variables of the same name in the outer scope

Rule 5.3: An identifier declared in an inner scope shall not
          hide an identifier declared in an outer scope

Fixed For:
    make LOG_LEVEL=50 PLAT=fvp

Change-Id: I67b6b05cbad4aeca65ce52981b4679b340604708
Signed-off-by: default avatarDaniel Boulby <daniel.boulby@arm.com>
      896a5902
  35. 11 Jun, 2018 1 commit
    • John Tsichritzis's avatar
      MISRA rule 21.15 fix · bdcd33a8
      John Tsichritzis authored 
      

    Rule 21.15: The pointer arguments to the Standard Library functions
    memcpy, memmove and memcmp shall be pointers to qualified or unqualified
    versions of compatible types.

    Basically that means that both pointer arguments must be of the same
    type. However, even if the pointers passed as arguments to the above
    functions are of the same type, Coverity still thinks it's a violation
    if we do pointer arithmetics directly at the function call. Thus the
    pointer arithmetic operations were moved outside of the function
    argument.

    First detected on the following configuration
            make PLAT=fvp LOG_LEVEL=50

    Change-Id: I8b912ec1bfa6f2d60857cb1bd453981fd7001b94
Signed-off-by: default avatarJohn Tsichritzis <john.tsichritzis@arm.com>
      bdcd33a8
  37. 08 Jun, 2018 1 commit