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  1. 29 Mar, 2021 8 commits
    • Aditya Angadi's avatar
      board/rdv1mc: initialize tzc400 controllers · f97b5795
      Aditya Angadi authored 
      

A TZC400 controller is placed inline on DRAM channels and regulates
the secure and non-secure accesses to both secure and non-secure
regions of the DRAM memory. Configure each of the TZC controllers
across the Chips.

For use by secure software, configure the first chip's trustzone
controller to protect the upper 16MB of the memory of the first DRAM
block for secure accesses only. The other regions are configured for
non-secure read write access. For all the remote chips, all the DRAM
regions are allowed for non-secure read and write access.
Signed-off-by: default avatarAditya Angadi <aditya.angadi@arm.com>
Change-Id: I809f27eccadfc23ea0ef64e2fd87f95eb8f195c1
      f97b5795
    • Aditya Angadi's avatar
      plat/sgi: allow access to TZC controller on all chips · 21803491
      Aditya Angadi authored 
      

On a multi-chip platform, the boot CPU on the first chip programs the
TZC controllers on all the remote chips. Define a memory region map for
the TZC controllers for all the remote chips and include it in the BL2
memory map table.

In addition to this, for SPM_MM enabled multi-chip platforms, increase
the number of mmap entries and xlat table counts for EL3 execution
context as well because the shared RAM regions and GIC address space of
remote chips are accessed.
Signed-off-by: default avatarAditya Angadi <aditya.angadi@arm.com>
Change-Id: I6f0b5fd22f9f28046451e382eef7f1f9258d88f7
      21803491
    • Aditya Angadi's avatar
      plat/sgi: define memory regions for multi-chip platforms · 05b5c417
      Aditya Angadi authored 
      

For multi-chip platforms, add a macro to define the memory regions on
chip numbers >1 and its associated access permissions. These memory
regions are marked with non-secure access.
Signed-off-by: default avatarAditya Angadi <aditya.angadi@arm.com>
Change-Id: If3d6180fd8ea61f45147c39d3140d694abf06617
      05b5c417
    • Thomas Abraham's avatar
      plat/sgi: allow access to nor2 flash and system registers from s-el0 · 5dae6bc7
      Thomas Abraham authored 
      

Allow the access of system registers and nor2 flash memory region
from s-el0. This allows the secure parititions residing at s-el0
to access these memory regions.
Signed-off-by: default avatarThomas Abraham <thomas.abraham@arm.com>
Change-Id: I3887a86770de806323fbde0d20fdc96eec6e0c3c
      5dae6bc7
    • Thomas Abraham's avatar
      plat/sgi: define default list of memory regions for dmc620 tzc · b4d548f1
      Thomas Abraham authored 
      

Define a default DMC-620 TZC memory region configuration and use it to
specify the TZC memory regions on sgi575, rdn1edge and rde1edge
platforms. The default DMC-620 TZC memory regions are defined
considering the support for secure paritition as well.
Signed-off-by: default avatarThomas Abraham <thomas.abraham@arm.com>
Change-Id: Iedee3e57d0d3de5b65321444da51ec990d3702db
      b4d548f1
    • Thomas Abraham's avatar
      plat/sgi: improve macros defining cper buffer memory region · d306eb80
      Thomas Abraham authored 
      

Remove the 'ARM_' prefix from the macros defining the CPER buffer memory
and replace it with 'CSS_SGI_' prefix. These macros are applicable only
for platforms supported within plat/sgi. In addition to this, ensure
that these macros are defined only if the RAS_EXTENSION build option is
enabled.
Signed-off-by: default avatarThomas Abraham <thomas.abraham@arm.com>
Change-Id: I44df42cded18d9d3a4cb13e5c990e9ab3194daee
      d306eb80
    • Thomas Abraham's avatar
      plat/sgi: refactor DMC-620 error handling SMC function id · 513ba5c9
      Thomas Abraham authored 
      

The macros defining the SMC function ids for DMC-620 error handling are
listed in the sgi_base_platform_def.h header file. But these macros are
not applicable for all platforms supported under plat/sgi. So move these
macro definitions to sgi_ras.c file in which these are consumed. While
at it, remove the AArch32 and error injection function ids as these are
unused.
Signed-off-by: default avatarThomas Abraham <thomas.abraham@arm.com>
Change-Id: I249b54bf4c1b1694188a1e3b297345b942f16bc9
      513ba5c9
    • Thomas Abraham's avatar
      plat/sgi: refactor SDEI specific macros · a8834474
      Thomas Abraham authored 
      

The macros specific to SDEI defined in the sgi_base_platform_def.h are
not applicable for all the platforms supported by plat/sgi. So refactor
the SDEI specific macros into a new header file and include this file on
only on platforms it is applicable on.
Signed-off-by: default avatarThomas Abraham <thomas.abraham@arm.com>
Change-Id: I0cb7125334f02a21cae1837cdfd765c16ab50bf5
      a8834474
  3. 26 Mar, 2021 1 commit
    • Bharat Gooty's avatar
      driver: brcm: add i2c driver · 48c6a6b6
      Bharat Gooty authored 
      

Broadcom I2C controller driver. Follwoing API's are supported:-
- i2c_init() Intialize ethe I2C controller
- i2c_probe()
- i2c_set_bus_speed() Set the I2C bus speed
- i2c_get_bus_speed() Get the current bus speed
- i2c_recv_byte() Receive one byte of data.
- i2c_send_byte() Send one byteof data
- i2c_read_byte() Read single byte of data
- i2c_read() Read multiple bytes of data
- i2c_write_byte Write single byte of data
- i2c_write() Write multiple bytes of data

This driver is verified by reading the DDR SPD data.
Signed-off-by: default avatarBharat Gooty <bharat.gooty@broadcom.com>
Change-Id: I2d7fe53950e8b12fab19d0293020523ff8b74e13
      48c6a6b6
  5. 25 Mar, 2021 1 commit
    • Andre Przywara's avatar
      allwinner: A64: Limit FDT checks to reduce code size · 8fa5592b
      Andre Przywara authored 
      

The upcoming refactoring to support the new H616 SoCs will push the A64
build over the edge, by using more than the 48KB of SRAM available.

To reduce the code size, set some libfdt options that aim to reduce
sanity checks (for saving code space):
- ASSUME_LATEST: only allow v17 DTBs (as created by dtc)
- ASSUME_NO_ROLLBACK: don't prepare for failed DT additions
- ASSUME_LIBFDT_ORDER: assume sane ordering, as done by dtc

Change-Id: I12c93ec09e7587c5ae71e54947f817c32ce5fd6d
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      8fa5592b
  7. 24 Mar, 2021 18 commits
  9. 23 Mar, 2021 1 commit
  11. 22 Mar, 2021 1 commit
  13. 19 Mar, 2021 1 commit
  15. 16 Mar, 2021 1 commit
  17. 15 Mar, 2021 1 commit
    • Olivier Deprez's avatar
      SPM: declare third cactus instance as UP SP · e96fc8e7
      Olivier Deprez authored 
      

The FF-A v1.0 spec allows two configurations for the number of EC/vCPU
instantiated in a Secure Partition:
-A MultiProcessor (MP) SP instantiates as many ECs as the number of PEs.
An EC is pinned to a corresponding physical CPU.
-An UniProcessor (UP) SP instantiates a single EC. The EC is migrated to
the physical CPU from which the FF-A call is originating.
This change permits exercising the latter case within the TF-A-tests
framework.
Signed-off-by: default avatarOlivier Deprez <olivier.deprez@arm.com>
Change-Id: I7fae0e7b873f349b34e57de5cea496210123aea0
      e96fc8e7
  19. 10 Mar, 2021 1 commit
  21. 09 Mar, 2021 1 commit
  23. 08 Mar, 2021 1 commit
  25. 03 Mar, 2021 4 commits