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  1. 31 Jan, 2019 7 commits
    • kalyani chidambaram's avatar
      Tegra210: SiP handlers to allow PMC access · fdc08e2e
      kalyani chidambaram authored 
      

This patch adds SiP handler for Tegra210 platforms to service
read/write requests for PMC block. None of the secure registers
are accessible to the NS world though.

Change-Id: I7dc1f10c6a6ee6efc642ddcfb1170fb36d3accff
Signed-off-by: default avatarkalyani chidambaram <kalyanic@nvidia.com>
      fdc08e2e
    • Varun Wadekar's avatar
      Tegra210: power off all DMA masters before System Suspend entry · 2d5560f9
      Varun Wadekar authored 
      

This patch puts all the DMA masters in reset before starting the System
Suspend sequence. This helps us make sure that there are no rogue agents
in the system trying to over-write the SC7 Entry Firmware with their own.

Change-Id: I7eb39999d229951e612fbfeb9f86c4efb8f98b5a
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      2d5560f9
    • Varun Wadekar's avatar
      Tegra: support for System Suspend using sc7entry-fw binary · 3ca3c27c
      Varun Wadekar authored 
      

This patch adds support to enter System Suspend on Tegra210 platforms
without the traditional BPMP firmware. The BPMP firmware will no longer
be supported on Tegra210 platforms and its functionality will be
divided across the CPU and sc7entry-fw.

The sc7entry-fw takes care of performing the hardware sequence required
to enter System Suspend (SC7 power state) from the COP. The CPU is required
to load this firmware to the internal RAM of the COP and start the sequence.
The CPU also make sure that the COP is off after cold boot and is only
powered on when we want to start the actual System Suspend sequence.

The previous bootloader loads the firmware to TZDRAM and passes its base and
size as part of the boot parameters. The EL3 layer is supposed to sanitize
the parameters before touching the firmware blob.

To assist the warmboot code with the PMIC discovery, EL3 is also supposed to
program PMC's scratch register #210, with appropriate values. Without these
settings the warmboot code wont be able to get the device out of System
Suspend.

Change-Id: I5a7b868512dbfd6cfefd55acf3978a1fd7ebf1e2
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      3ca3c27c
    • Varun Wadekar's avatar
      Tegra210: remove support for cluster power down · 93e3b0f3
      Varun Wadekar authored 
      

This patch removes support for powering down a CPU cluster on
Tegra210 platforms as none of them actually use it.

Change-Id: I9665634cf2b5b7b8a1b5a2700cae152dc9165fe3
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      93e3b0f3
    • Varun Wadekar's avatar
      Tegra210: support for cluster idle from the CPU · 7db077f2
      Varun Wadekar authored 
      

This patch adds support to enter/exit to/from cluster idle power
state on Tegra210 platforms that do not load BPMP firmware.

The CPU initates the cluster idle sequence on the last standing
CPU, by following these steps:

Entry
-----
* stop other CPUs from waking up
* program the PWM pinmux to tristate for OVR PMIC
* program the flow controller to enter CC6 state
* skip L1 $ flush during cluster power down, as L2 $ is inclusive
  of L1 $ on Cortex-A57 CPUs

Exit
----
* program the PWM pinmux to un-tristate for OVR PMIC
* allow other CPUs to wake up

This patch also makes sure that cluster idle state entry is not
enabled until CL-DVFS is ready.

Change-Id: I54cf31bf72b4a09d9bf9d2baaed6ee5a963c7808
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      7db077f2
    • Varun Wadekar's avatar
      Tegra210: Enable WDT_CPU interrupt for FIQ Debugger · 51a5e593
      Varun Wadekar authored 
      

This patch enables the watchdog timer's interrupt as an FIQ
interrupt to the CPU. The interrupt generated by the watchdog
is connected to the flow controller for power management reasons,
and needs to be routed to the GICD for it to reach the CPU.

Change-Id: I9437b516da2c5d763eca72694ed7f3c7389b3d9e
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      51a5e593
    • Varun Wadekar's avatar
      Tegra: fiq_glue: support to handle LEGACY_FIQ PPIs for Tegra SoCs · d16b045c
      Varun Wadekar authored 
      

This patch adds support to handle secure PPIs for Tegra watchdog timers. This
functionality is currently protected by the ENABLE_WDT_LEGACY_FIQ_HANDLING
configuration variable and is only enabled for Tegra210 platforms, for now.

Change-Id: I0752ef54a986c58305e1bc8ad9be71d4a8bbd394
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      d16b045c
  3. 23 Jan, 2019 2 commits
  5. 18 Jan, 2019 8 commits
  7. 16 Jan, 2019 7 commits
  9. 04 Jan, 2019 1 commit
    • Antonio Nino Diaz's avatar
      Sanitise includes across codebase · 09d40e0e
      Antonio Nino Diaz authored 
      Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca339

 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      09d40e0e
  11. 18 Dec, 2018 1 commit
  13. 17 Feb, 2018 1 commit
    • Andreas Färber's avatar
      tegra: Fix mmap_region_t struct mismatch · 28db3e96
      Andreas Färber authored 
      Commit fdb1964c

 ("xlat: Introduce
MAP_REGION2() macro") added a granularity field to mmap_region_t.

Tegra platforms were using the v2 xlat_tables implementation in
common/tegra_common.mk, but v1 xlat_tables.h headers in soc/*/plat_setup.c
where arrays are being defined. This caused the next physical address to
be read as granularity, causing EINVAL error and triggering an assert.

Consistently use xlat_tables_v2.h header to avoid this.

Fixes ARM-software/tf-issues#548.
Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
      28db3e96
  15. 14 Jul, 2017 1 commit
  17. 14 Jun, 2017 1 commit
  19. 03 May, 2017 1 commit
  21. 01 May, 2017 2 commits
  23. 20 Mar, 2017 1 commit
  25. 07 Mar, 2017 1 commit
    • Varun Wadekar's avatar
      Tegra210: enable errata for Cortex-A57 and Cortex-A53 CPUs · 1f38d3c9
      Varun Wadekar authored 
      

This patch enables the following erratas for the Tegra210 SoC:

* Cortex-A57
=============
- A57_DISABLE_NON_TEMPORAL_HINT
- ERRATA_A57_826974
- ERRATA_A57_826977
- ERRATA_A57_828024
- ERRATA_A57_829520
- ERRATA_A57_833471

* Cortex-A53
=============
- A53_DISABLE_NON_TEMPORAL_HINT
- ERRATA_A53_826319
- ERRATA_A53_836870

Tegra210 uses Cortex-A57 revision: r1p1 and Cortex-A53 revision: r0p2.
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      1f38d3c9
  27. 02 Mar, 2017 3 commits
  29. 28 Feb, 2017 1 commit
    • Varun Wadekar's avatar
      Tegra: GIC: enable FIQ interrupt handling · d3360301
      Varun Wadekar authored 
      

Tegra chips support multiple FIQ interrupt sources. These interrupts
are enabled in the GICD/GICC interfaces by the tegra_gic driver. A
new FIQ handler would be added in a subsequent change which can be
registered by the platform code.

This patch adds the GIC programming as part of the tegra_gic_setup()
which now takes an array of all the FIQ interrupts to be enabled for
the platform. The Tegra132 and Tegra210 platforms right now do not
register for any FIQ interrupts themselves, but will definitely use
this support in the future.

Change-Id: I0ea164be901cd6681167028fea0567399f18d4b8
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      d3360301
  31. 23 Feb, 2017 2 commits