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These sections of code are only needed for the coherency workaround
used for AM65x, if this workaround is not needed then this code
is not either. Mark it off to keep it separated from the rest of
the PSCI implementation.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I113ca6a2a1f7881814ab0a64e5bac57139bc03ef

To make the USE_COHERENT_MEM option work we need to add an entry for the
area to our memory map table. Also fixup the alignment here.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I1c05477a97646ac73846a711bc38d3746628d847

The size of the RO data area was calculated by subtracting the area end
address from itself and not the base address due to a typo. Fix this
here.

Note, this was noticed at a glance thanks to the new aligned formating
of this table.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I994022ac9fc95dc5e37a420714da76081c61cce7

This macro was used when many of these functions were stubbed out,
the macro is not used anymore, remove it.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Ida33f92fe3810a89e6e51faf6e93c1d2ada1a2ee

* changes:
  Console: Remove Arm console unregister on suspend
  Console: Allow to register multiple times

* changes:
  ti: k3: drivers: ti_sci: Retry message receive on bad sequence ID
  ti: k3: drivers: ti_sci: Cleanup sequence ID usage
  ti: k3: drivers: sec_proxy: Use direction definitions
  ti: k3: drivers: sec_proxy: Fix printf format specifiers

* changes:
  ti: k3: common: Align elements of map region table
  ti: k3: common: Enable SEPARATE_CODE_AND_RODATA by default
  ti: k3: common: Remove shared RAM space
  ti: k3: common: Drop _ADDRESS from K3_USART_BASE to match other defines

Change-Id: Ie649b3c367a93db057eeaee7e83fa3e43f8c2607
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

It removes the need to unregister the console on system suspend.

Change-Id: Ic9311a242a4a9a778651f7e6380bd2fc0964b2ce
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

When we get a sequence ID that does not match what we expect then the we
are looking at is not the one we are expecting and so we error out. We
can also assume this message is a stale message left in the queue, in
this case we can read in the next message and check again for our
message. Switch to doing that here. We only retry a set number of times
so we don't lock the system if our message is actually lost and will
never show up.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I6c8186ccc45e646d3ba9d431f7d4c451dcd70c5c

The sequence ID can be set with a message to identify it when it is
responded to in the response queue. We assign each message a number and
check for this same number to detect response mismatches.

Start this at 0 and increase it by one for each message sent, even ones
that do not request or wait for a response as one may still be delivered
in some cases and we want to detect this.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I72b4d1ef98bf1c1409d9db9db074af8dfbcd83ea

The direction of a thread should be explicitly compared to avoid
confusion. Also fixup message wording based on this direction.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Ia3cf9413cd23af476bb5d2e6d70bee15234cbd11

The ID of a thread is not used outside for printing it out when
something goes wrong. The specifier used is also not consistent.
Instead of storing the thread ID, store its name and print that.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Id137c2f8dfdd5c599e220193344ece903f80af7b

* changes:
  stm32mp1: add OP-TEE support
  stm32mp1: fix TZC400 configuration against non-secure DDR
  stm32mp1: remove useless define
  stm32mp: split stm32mp_io_setup function

Support booting OP-TEE as BL32 boot stage and secure runtime
service.

OP-TEE executes in internal RAM and uses a secure DDR area to store
the pager pagestore. Memory mapping and TZC are configured accordingly
prior OP-TEE boot. OP-TEE image is expected in OP-TEE v2 format where
a header file describes the effective boot images. This change
post processes header file content to get OP-TEE load addresses
and set OP-TEE boot arguments.

Change-Id: I02ef8b915e4be3e95b27029357d799d70e01cd44
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

This change disables secure accesses to non-secure DDR which are useless.
TF-A already maps non-secure memory with non-secure permissions thanks
to the MMU.

This change also corrects some inline comments.

Change-Id: Id4c20c9ee5c95a666dae6b7446ed80baf2d53fb0
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

Remove STM32MP_DDR_SPEED_DFLT that is not used in STM32MP1 TF-A code.

Change-Id: I780cdc4e93a8a9d997d50f67cfc582acd4a353d6
Signed-off-by: Yann Gautier <yann.gautier@st.com>

A new static function boot_mmc is created to simplify code maintenance
of stm32mp_io_setup.

Change-Id: I5c416e567e7e174fb1c2b435925a983c9c55fc40
Signed-off-by: Yann Gautier <yann.gautier@st.com>

* changes:
  plat/arm: introduce wrapper functions to setup secure watchdog
  drivers/sbsa: add sbsa watchdog driver

This is only a formatting change but makes it instantly clear how each
region is set. This is over 80 chars and the MT_RO are not strictly
needed but this section very important to get right so make readability
the priority here.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I2432deda05d4502b3478170296b5da43f26ad8e6

This should be more secure and looks a bit cleaner.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Ie5eaf0234b211ba02631cf5eab5faa1402a34461

We don't use this for anything right now, remove it.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I11505d01834f7ff1fdba46fda0acbb3b56fc9b66

This makes definitions more consistent, plus helps alignment.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I38fcdd76207586613d9934c9dc83d7a347e9e0fc

This patch forces all cacheable atomic instructions to be near, which
improves performance in highly contended parallelized use-cases.

Change-Id: I93fac62847f4af8d5eaaf3b52318c30893e947d3
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

Change-Id: I22568caf83b9846cd7b59241fcec34a395825399
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

The BL1 stage setup code for ARM platforms sets up the SP805 watchdog
controller as the secure watchdog. But not all ARM platforms use SP805
as the secure watchdog controller.

So introduce two new ARM platform code specific wrapper functions to
start and stop the secure watchdog. These functions then replace the
calls to SP805 driver in common BL1 setup code. All the ARM platforms
implement these wrapper functions by either calling into SP805 driver
or the SBSA watchdog driver.

Change-Id: I1a9a11b124cf3fac2a84f22ca40acd440a441257
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

Add a driver for configuring the SBSA Generic Watchdog which aids in
the detection of errant system behaviour.

Change-Id: I5a1e7149c69fd8b85be7dfbcf511f431339946f4
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

Under certain near idle conditions, DSU may miss response transfers on
the ACE master or Peripheral port, leading to deadlock. This workaround
disables high-level clock gating of the DSU to prevent this.

Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

Change-Id: I50708f6ccc33059fbfe6d36fd66351f0b894311f
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

Under specific conditions, the processor might issue an eviction and an
L2 cache clean operation to the interconnect in the wrong order. Set
the CPUACTLR.ENDCCASCI bit to 1 to avoid this.

Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

There is a bug in the shared heap implementation for SGM. Until the bug
is solved, the default implementation is used.

Change-Id: I010911a3f00ed860f742b14daad1d99b9e7ce711
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

* changes:
  Mbed TLS: Remove weak heap implementation
  sgm: Fix bl2 sources

* changes:
  doc: Clarify cert_create build when USE_TBBR_DEFS=0
  plat/sgm: Remove redundant platform_oid.h

On Cortex A9 an errata can cause the processor to violate the rules for
speculative fetches when the MMU is off but branch prediction has not
been disabled. The workaround for this is to execute an Invalidate
Entire Branch Prediction Array (BPIALL) followed by a DSB.

see:http://arminfo.emea.arm.com/help/topic/com.arm.doc.uan0009d/UAN0009_cortex_a9_errata_r4.pdf


for more details.

Change-Id: I9146c1fa7563a79f4e15b6251617b9620a587c93
Signed-off-by: Joel Hutton <Joel.Hutton@arm.com>

* changes:
  rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.3
  rcar_gen3: drivers: Change to restore timer counter value at resume
  rcar_gen3: drivers: pwrc: Add DBSC4 setting before self-refresh mode
  rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.2
  rcar_gen3: drivers: ddr: Update DDR setting rev.0.35
  rcar_gen3: drivers: qos: change subslot cycle
  rcar_gen3: drivers: board: Add new board revision for H3ULCB
  rcar_gen3: plat: Change periodic write DQ training option.