- 04 Feb, 2021 1 commit
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Maxim Uvarov authored
Secure pl061 qemu driver allows to rize the GPIO pin from the secure world to reboot and power down virtual machine. Do not define secure-gpio for sbsa-ref platform due to reboot is done via sbsa-ec watchdog. Signed-off-by:Maxim Uvarov <maxim.uvarov@linaro.org> Change-Id: I508d7c5cf4c75cb169b34b00682a76f6761d3869
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- 14 Jan, 2021 4 commits
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Lauren Wehrmeister authored
* changes: Workaround for Cortex N1 erratum 1946160 Workaround for Cortex A78 erratum 1951500
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Madhukar Pappireddy authored
* changes: plat: renesas: common: Include ulcb_cpld.h conditionally plat: renesas: Move to common plat: renesas: aarch64: Move to common drivers: renesas: Move ddr/qos/qos header files drivers: renesas: rpc: Move to common drivers: renesas: avs: Move to common drivers: renesas: auth: Move to common drivers: renesas: dma: Move to common drivers: renesas: watchdog: Move to common drivers: renesas: rom: Move to common drivers: renesas: delay: Move to common drivers: renesas: console: Move to common drivers: renesas: pwrc: Move to common drivers: renesas: io: Move to common drivers: renesas: eMMC: Move to common
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Madhukar Pappireddy authored
* changes: drivers: renesas: Move plat common sources plat: renesas: Move headers and assembly files to common folder plat: renesas: rcar: include: Code cleanup plat: renesas:rcar: Fix checkpatch warnings plat: renesas: rcar: Fix checkpatch warnings plat: renesas:rcar: Code cleanup plat: renesas: rcar: Fix coding style
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Madhukar Pappireddy authored
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- 13 Jan, 2021 27 commits
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johpow01 authored
Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0, r2p0, r3p0, r3p1, r4p0, and r4p1. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This issue is present starting from r0p0 but this workaround applies to revisions r3p0, r3p1, r4p0, and r4p1, for previous revisions there is no workaround. SDEN can be found here: https://documentation-service.arm.com/static/5fa9304cd8dacc30eded464f Signed-off-by:
John Powell <john.powell@arm.com> Change-Id: I36e4d6728c275f1c2477dcee9b351077cf7c53e4
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johpow01 authored
Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This workaround works on revisions r1p0 and r1p1, in r0p0 there is no workaround. SDEN can be found here: https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e Signed-off-by:
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Aditya Angadi authored
Move RD-V1 platform to use version of FVP_RD_Daniel from 11.10 build 36 to 11.13 build 10 Signed-off-by:Aditya Angadi <aditya.angadi@arm.com> Change-Id: I9622c03d342bb780234dec8ffe4ab11d8069acab
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Biju Das authored
Include header ulcb_cpld.h in plat_pm.c only if RCAR_GEN3_ULCB is enabled. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: Ie89223097c608265c50e32778e8df28feed82480
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Biju Das authored
Move rcar plat code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by:
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Biju Das authored
Move plat aarch64 code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by:
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Biju Das authored
Move DDR/QoS/PFC header files, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by:
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Biju Das authored
Move rpc driver code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by:
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Biju Das authored
Move avs driver code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by:
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Biju Das authored
Move authentication driver code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by:
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Biju Das authored
Move dma driver code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by:
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Biju Das authored
Move watch driver code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by:
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Biju Das authored
Move plat common sources to common directory, so that same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by:
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Biju Das authored
Move rom driver code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by:
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Biju Das authored
Create a common directory and move the header and assembly files so that the common code can be used by both Renesas R-Car Gen3 and RZ/G2 platforms. Signed-off-by:
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Biju Das authored
Move delay driver code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by:
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Biju Das authored
This patch fixes checkpatch warnings and replaces TAB with space after #define macros. Signed-off-by:
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Biju Das authored
Move console/scif driver code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by:
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Biju Das authored
Fix checkpatch warnings. Signed-off-by:
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Biju Das authored
Move pwrc driver code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by:
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Biju Das authored
Fix checkpatch warnings. Signed-off-by:
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Biju Das authored
Move io driver code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by:
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Biju Das authored
Sort the header includes alphabetically, fix typos and drop unneeded TAB and replace it with space Signed-off-by:
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Biju Das authored
Move eMMC driver code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by:
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Biju Das authored
Sort the header includes alphabetically and fix checkpatch warnings. Signed-off-by:
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Manish Pandey authored
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Masahisa Kojima authored
This implements support for UEFI secure variable storage using standalone MM framework on qemu_sbsa platform. Non-secure shared memory between UEFI and standalone MM is allocated at the top of DRAM. DRAM size of qemu_sbsa varies depends on the QEMU parameter, so the non-secure shared memory is allocated by trusted firmware and passed the base address and size to UEFI through device tree "/reserved-memory" node. Change-Id: I367191f408eb9850b7ec7761ee346b014c539767 Signed-off-by:Masahisa Kojima <masahisa.kojima@linaro.org>
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- 12 Jan, 2021 8 commits
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bipin.ravi authored
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johpow01 authored
Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1 register, there is a small performance cost (<0.5%) for setting this bit. SDEN can be found here: https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e Signed-off-by:
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Madhukar Pappireddy authored
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Will Wong authored
Add ability to support PS and System reset after idling the APU, by reading the restart scope from the PMU. Signed-off-by:
Will Wong <willw@xilinx.com> Signed-off-by:
Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: I23c01725d8ebb71ad34be02ab204411b93620702
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Lauren Wehrmeister authored
Merge "plat: marvell: armada: a3k: improve 4GB DRAM usage from 3.375 GB to 3.75 GB" into integration
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Manish Pandey authored
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Manish Pandey authored
* changes: plat/arm: rename rddanielxlr to rdv1mc plat/arm: rename rddaniel to rdv1
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Rajan Vaja authored
ATF is not checking PM version. Add version check in such a way that it is compatible with current and newer version of PM. Signed-off-by:
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