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adam.huang
Arm Trusted Firmware
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c3e57739043d8557ce21fbb6627a6e09fbd70e5c
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Created with Raphaël 2.2.0
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Tegra: platform handler to relocate BL32 image
Tegra: common: improve cyclomatic complexity
Tegra210: secure PMC hardware block
Tegra: delay_timer: support for physical secure timer
include: move MHZ_TICKS_PER_SEC to utils_def.h
Tegra194: memctrl: lock mc stream id security config
Tegra210: resume PMC hardware block for all platforms
Tegra: macro for legacy WDT FIQ handling
Tegra186: enable higher performance non-cacheable load forwarding
Tegra210: enable higher performance non-cacheable load forwarding
cpus: higher performance non-cacheable load forwarding
Use consistent SMCCC error code
Merge "intel: Fix Coverity Scan Defects" into integration
intel: Fix Coverity Scan Defects
Merge "Update docs with PMU security information" into integration
Merge changes I72846d86,I70c3d873,If675796a,I0dbf8091,Ie4f3ac83, ... into integration
Merge "TBBR: Reduce size of hash buffers when possible" into integration
Merge "TBBR: Reduce size of ECDSA key buffers" into integration
Merge "corstone700: fdts: using DDR memory and XIP rootfs" into integration
board/rddaniel: intialize tzc400 controllers
plat/arm/tzc: add support to configure multiple tzc400
plat/arm: allow boards to specify second DRAM Base address
plat/arm: allow boards to define PLAT_ARM_TZC_FILTERS
Merge changes I5ca7a004,Ibcb336a2 into integration
board/rdn1edge: use CREATE_SEQ helper macro to compare chip count
build_macros: add create sequence helper function
corstone700: fdts: using DDR memory and XIP rootfs
Merge changes from topic "corstone700" into integration
Merge "coverity: fix MISRA violations" into integration
Merge "FVP: Fix BL31 load address and image size for RESET_TO_BL31=1" into integration
coverity: fix MISRA violations
Merge changes I4e95678f,Ia7c28704,I1bb04bb4,I93d96dca,I50aef5dd into integration
Add Matterhorn CPU lib
Add CPULib for Klein Core
FVP: Fix BL31 load address and image size for RESET_TO_BL31=1
TBBR: Reduce size of hash buffers when possible
TBBR: Reduce size of ECDSA key buffers
corstone700: set UART clocks to 32MHz
corstone700: clean-up as per coding style guide
Corstone700: add support for mhuv2 in arm TF-A
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