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DSU: Implement workaround for errata 798953
Louis Mayencourt authored
Under certain near idle conditions, DSU may miss response transfers on
the ACE master or Peripheral port, leading to deadlock. This workaround
disables high-level clock gating of the DSU to prevent this.

Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b
Signed-off-by: default avatarLouis Mayencourt <louis.mayencourt@arm.com>
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