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intel: SIP: increase FPGA_CONFIG_SIZE to 32 MB
Richard Gong authored 
Increase INTEL_SIP_SMC_FPGA_CONFIG_SIZE from 16 to 32MB. We need higher
pre-reserved memory size between Intel service layer and secure monitor
software so we can handle JIC file authorization.
Signed-off-by: default avatarRichard Gong <richard.gong@intel.com>
Change-Id: Ibab4e42e4b7b93a4cf741e60ec9439359ba0a64c
1ae7b6f6
Name Last commit Last update
bl1 Increase type widths to satisfy width requirements
bl2 TF-A: Add support for Measured Boot driver in BL1 and BL2
bl2u linker_script: move .data section to bl_common.ld.h
bl31 Increase type widths to satisfy width requirements
bl32 Merge "Increase type widths to satisfy width requirements" into integration
common Merge "Increase type widths to satisfy width requirements" into integration
docs Merge "docs: marvell: update ddr3 build instructions" into integration
drivers Merge "Increase type widths to satisfy width requirements" into integration
fdts plat: tc0: Add TZC DRAM1 region for SPMC and trusted OS
include plat: arm: Make BL32_BASE platform dependent when SPD_spmd is enabled
lib lib: el3_runtime: Fix SPE system registers in el2_sysregs_context
make_helpers lib: el3_runtime: Conditionally save/restore EL2 NEVE registers
plat intel: SIP: increase FPGA_CONFIG_SIZE to 32 MB
services spmd: Fix signedness comparison warning
tools Update makefile to build fiptool for Windows
.checkpatch.conf Re-apply GIT_COMMIT_ID check for checkpatch
.editorconfig doc: Final, pre-release fixes and updates
.gitignore Ignore the ctags file
.gitreview Specify integration as the default branch for git-review
Makefile lib: el3_runtime: Conditionally save/restore EL2 NEVE registers
dco.txt Drop requirement for CLA in contribution.md
license.rst doc: De-duplicate readme and license files
readme.rst doc: Formatting fixes for readme.rst
readme.rst

Trusted Firmware-A

Trusted Firmware-A (TF-A) is a reference implementation of secure world software for Arm A-Profile architectures (Armv8-A and Armv7-A), including an Exception Level 3 (EL3) Secure Monitor. It provides a suitable starting point for productization of secure world boot and runtime firmware, in either the AArch32 or AArch64 execution states.

TF-A implements Arm interface standards, including:

The code is designed to be portable and reusable across hardware platforms and software models that are based on the Armv8-A and Armv7-A architectures.

In collaboration with interested parties, we will continue to enhance TF-A with reference implementations of Arm standards to benefit developers working with Armv7-A and Armv8-A TrustZone technology.

Users are encouraged to do their own security validation, including penetration testing, on any secure world code derived from TF-A.

More Info and Documentation

To find out more about Trusted Firmware-A, please view the full documentation that is available through trustedfirmware.org.

Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.