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Optimize SMCCC_ARCH_WORKAROUND_1 on Cortex A57/A72/A73 and A75
Dimitris Papastamos authored
This patch implements a fast path for this SMC call on affected PEs by
detecting and returning immediately after executing the workaround.

NOTE: The MMU disable/enable workaround now assumes that the MMU was
enabled on entry to EL3.  This is a valid assumption as the code turns
on the MMU after reset and leaves it on until the core powers off.

Change-Id: I13c336d06a52297620a9760fb2461b4d606a30b3
Signed-off-by: default avatarDimitris Papastamos <dimitris.papastamos@arm.com>
1d6d47a8
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