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Merge "Aarch64: Fix SCTLR bit definitions" into integration
John Tsichritzis authored
274e8714
Name Last commit Last update
bl1 Add support for Branch Target Identification
bl2 bl2_el3: clean up linker script
bl2u Apply stricter speculative load restriction
bl31 Add support for Branch Target Identification
bl32 Add support for Branch Target Identification
common Correctly check for support of Address Authentication
docs Rename Cortex-Deimos to Cortex-A77
drivers driver: synopsys: emmc: Do not change FIFO TH as this breaks some platforms
fdts fdts: stm32mp1: realign device tree files with internal devs
include Merge "Aarch64: Fix SCTLR bit definitions" into integration
lib Rename Cortex-Deimos to Cortex-A77
make_helpers Remove MULTI_CONSOLE_API flag and references to it
plat Merge "plat/intel: Fix SMPLSEL for MMC" into integration
services services/spm: Fix service UUID lookup
tools tools/fiptool: Add Makefile.msvc to build on Windows.
.checkpatch.conf Change checkpatch.conf after migration to tf.org
.editorconfig Add .editorconfig file
.gitignore meson/gxl: Add tool to create bl31 bootable images
Makefile Remove MULTI_CONSOLE_API flag and references to it
dco.txt Drop requirement for CLA in contribution.md
license.rst doc: Use proper note and warning annotations
readme.rst Rename Cortex-Deimos to Cortex-A77
readme.rst

Trusted Firmware-A - version 2.1

Trusted Firmware-A (TF-A) provides a reference implementation of secure world software for Armv7-A and Armv8-A, including a Secure Monitor executing at Exception Level 3 (EL3). It implements various Arm interface standards, such as:

Where possible, the code is designed for reuse or porting to other Armv7-A and Armv8-A model and hardware platforms.

This release provides a suitable starting point for productization of secure world boot and runtime firmware, in either the AArch32 or AArch64 execution states.

Users are encouraged to do their own security validation, including penetration testing, on any secure world code derived from TF-A.

Arm will continue development in collaboration with interested parties to provide a full reference implementation of Secure Monitor code and Arm standards to the benefit of all developers working with Armv7-A and Armv8-A TrustZone technology.

1.   Documentation contents

The Trusted Firmware-A Documentation Contents page contains an overview of the documentation that is available, with links to facilitate easier browsing.

2.   License

The software is provided under a BSD-3-Clause license. Contributions to this project are accepted under the same license with developer sign-off as described in the Contributing Guidelines.

This project contains code from other projects as listed below. The original license text is included in those source files.

  • The libc source code is derived from FreeBSD and SCC. FreeBSD uses various BSD licenses, including BSD-3-Clause and BSD-2-Clause. The SCC code is used under the BSD-3-Clause license with the author's permission.
  • The libfdt source code is disjunctively dual licensed (GPL-2.0+ OR BSD-2-Clause). It is used by this project under the terms of the BSD-2-Clause license. Any contributions to this code must be made under the terms of both licenses.
  • The LLVM compiler-rt source code is disjunctively dual licensed (NCSA OR MIT). It is used by this project under the terms of the NCSA license (also known as the University of Illinois/NCSA Open Source License), which is a permissive license compatible with BSD-3-Clause. Any contributions to this code must be made under the terms of both licenses.
  • The zlib source code is licensed under the Zlib license, which is a permissive license compatible with BSD-3-Clause.
  • Some STMicroelectronics platform source code is disjunctively dual licensed (GPL-2.0+ OR BSD-3-Clause). It is used by this project under the terms of the BSD-3-Clause license. Any contributions to this code must be made under the terms of both licenses.

3.   Functionality

  • Initialization of the secure world, for example exception vectors, control registers and interrupts for the platform.
  • Library support for CPU specific reset and power down sequences. This includes support for errata workarounds and the latest Arm DynamIQ CPUs.
  • Drivers to enable standard initialization of Arm System IP, for example Generic Interrupt Controller (GIC), Cache Coherent Interconnect (CCI), Cache Coherent Network (CCN), Network Interconnect (NIC) and TrustZone Controller (TZC).
  • A generic SCMI driver to interface with conforming power controllers, for example the Arm System Control Processor (SCP).
  • SMC (Secure Monitor Call) handling, conforming to the SMC Calling Convention using an EL3 runtime services framework.
  • PSCI library support for CPU, cluster and system power management use-cases. This library is pre-integrated with the AArch64 EL3 Runtime Software, and is also suitable for integration with other AArch32 EL3 Runtime Software, for example an AArch32 Secure OS.
  • A minimal AArch32 Secure Payload (SP_MIN) to demonstrate PSCI library integration with AArch32 EL3 Runtime Software.
  • Secure Monitor library code such as world switching, EL1 context management and interrupt routing. When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the AArch64 EL3 Runtime Software must be integrated with a Secure Payload Dispatcher (SPD) component to customize the interaction with the SP.
  • A Test SP and SPD to demonstrate AArch64 Secure Monitor functionality and SP interaction with PSCI.
  • SPDs for the OP-TEE Secure OS, NVIDIA Trusted Little Kernel and Trusty Secure OS.
  • A Trusted Board Boot implementation, conforming to all mandatory TBBR requirements. This includes image authentication, Firmware Update (or recovery mode), and packaging of the various firmware images into a Firmware Image Package (FIP).
  • Pre-integration of TBB with the Arm CryptoCell product, to take advantage of its hardware Root of Trust and crypto acceleration services.
  • Reliability, Availability, and Serviceability (RAS) functionality, including
    • A Secure Partition Manager (SPM) to manage Secure Partitions in Secure-EL0, which can be used to implement simple management and security services.
    • An SDEI dispatcher to route interrupt-based SDEI events.
    • An Exception Handling Framework (EHF) that allows dispatching of EL3 interrupts to their registered handlers, to facilitate firmware-first error handling.
  • A dynamic configuration framework that enables each of the firmware images to be configured at runtime if required by the platform. It also enables loading of a hardware configuration (for example, a kernel device tree) as part of the FIP, to be passed through the firmware stages.
  • Support for alternative boot flows, for example to support platforms where the EL3 Runtime Software is loaded using other firmware or a separate secure system processor, or where a non-TF-A ROM expects BL2 to be loaded at EL3.
  • Support for the GCC, LLVM and Arm Compiler 6 toolchains.
  • Support for combining several libraries into a "romlib" image that may be shared across images to reduce memory footprint. The romlib image is stored in ROM but is accessed through a jump-table that may be stored in read-write memory, allowing for the library code to be patched.
  • A prototype implementation of a Secure Partition Manager (SPM) that is based on the SPCI Alpha 1 and SPRT draft specifications.
  • Support for ARMv8.3 pointer authentication in the normal and secure worlds. The use of pointer authentication in the normal world is enabled whenever architectural support is available, without the need for additional build flags. Use of pointer authentication in the secure world remains an experimental configuration at this time and requires the ENABLE_PAUTH build flag to be set.
  • Position-Independent Executable (PIE) support. Initially for BL31 only, with further support to be added in a future release.

For a full description of functionality and implementation details, please see the Firmware Design and supporting documentation. The Change Log provides details of changes made since the last release.

4.   Platforms

Various AArch32 and AArch64 builds of this release have been tested on r0, r1 and r2 variants of the Juno Arm Development Platform.

The latest version of the AArch64 build of TF-A has been tested on the following Arm FVPs without shifted affinities, and that do not support threaded CPU cores (64-bit host machine only).

The FVP models used are Version 11.6 Build 45, unless otherwise stated.

  • FVP_Base_AEMv8A-AEMv8A
  • FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502
  • FVP_Base_RevC-2xAEMv8A
  • FVP_Base_Cortex-A32x4
  • FVP_Base_Cortex-A35x4
  • FVP_Base_Cortex-A53x4
  • FVP_Base_Cortex-A55x4+Cortex-A75x4
  • FVP_Base_Cortex-A55x4
  • FVP_Base_Cortex-A57x1-A53x1
  • FVP_Base_Cortex-A57x2-A53x4
  • FVP_Base_Cortex-A57x4-A53x4
  • FVP_Base_Cortex-A57x4
  • FVP_Base_Cortex-A72x4-A53x4
  • FVP_Base_Cortex-A72x4
  • FVP_Base_Cortex-A73x4-A53x4
  • FVP_Base_Cortex-A73x4
  • FVP_Base_Cortex-A75x4
  • FVP_Base_Cortex-A76x4
  • FVP_Base_Cortex-A76AEx4
  • FVP_Base_Cortex-A76AEx8
  • FVP_Base_Cortex-A77x4 (Version 11.7 build 36)
  • FVP_Base_Neoverse-N1x4
  • FVP_CSS_SGI-575 (Version 11.3 build 42)
  • FVP_CSS_SGM-775 (Version 11.3 build 42)
  • FVP_RD_E1Edge (Version 11.3 build 42)
  • FVP_RD_N1Edge
  • Foundation_Platform

The latest version of the AArch32 build of TF-A has been tested on the following Arm FVPs without shifted affinities, and that do not support threaded CPU cores (64-bit host machine only).

  • FVP_Base_AEMv8A-AEMv8A
  • FVP_Base_Cortex-A32x4

NOTE: The FVP_Base_RevC-2xAEMv8A FVP only supports shifted affinities.

The Foundation FVP can be downloaded free of charge. The Base FVPs can be licensed from Arm. See the Arm FVP website.

All the above platforms have been tested with Linaro Release 18.04.

This release also contains the following platform support:

  • Allwinner sun50i (A64, H5, and H6) SoCs
  • Amlogic Meson S905 (GXBB)
  • Amlogic Meson S905x (GXL)
  • Arm Juno Software Development Platform
  • Arm Neoverse N1 System Development Platform (N1SDP)
  • Arm Neoverse Reference Design N1 Edge (RD-N1-Edge) FVP
  • Arm Neoverse Reference Design E1 Edge (RD-E1-Edge) FVP
  • Arm SGI-575 and SGM-775
  • Arm Versatile Express FVP
  • HiKey, HiKey960 and Poplar boards
  • Intel Stratix 10 SoC FPGA
  • Marvell Armada 3700 and 8K
  • MediaTek MT6795 and MT8173 SoCs
  • NVIDIA T132, T186 and T210 SoCs
  • NXP QorIQ LS1043A, i.MX8MM, i.MX8MQ, i.MX8QX, i.MX8QM and i.MX7Solo WaRP7
  • QEMU
  • Raspberry Pi 3
  • Renesas R-Car Generation 3
  • RockChip RK3328, RK3368 and RK3399 SoCs
  • Socionext UniPhier SoC family and SynQuacer SC2A11 SoCs
  • STMicroelectronics STM32MP1
  • Texas Instruments K3 SoCs
  • Xilinx Versal and Zynq UltraScale + MPSoC

5.   Still to come

  • Support for additional platforms.
  • Refinements to Position Independent Executable (PIE) support.
  • Refinements to the SPCI-based SPM implementation as the draft SPCI and SPRT specifications continue to evolve.
  • Documentation enhancements.
  • Ongoing support for new architectural features, CPUs and System IP.
  • Ongoing support for new Arm system architecture specifications.
  • Ongoing security hardening, optimization and quality improvements.

For a full list of detailed issues in the current code, please see the Change Log and the issue tracker.

6.   Getting started

See the User Guide for instructions on how to download, install, build and use TF-A with the Arm FVPs.

See the Firmware Design for information on how TF-A works.

See the Porting Guide as well for information about how to use this software on another Armv7-A or Armv8-A platform.

See the Contributing Guidelines for information on how to contribute to this project and the Acknowledgments file for a list of contributors to the project.

6.1.   Contact us

We welcome any feedback on TF-A. If you think you have found a security vulnerability, please report this using the process defined in the TF-A Security Center. For all other feedback, you can use either the issue tracker or our mailing list.

Arm licensees may contact Arm directly via their partner managers.

7.   Security advisories

Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.