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fix(plat/qemu): (NS_DRAM0_BASE + NS_DRAM0_SIZE) ADDR overflow 32bit
lwpDarren authored 
after this commit: If15cf3b9d3e2e7876c40ce888f22e887893fe696
plat/qemu/common/qemu_pm.c:116:	    (entrypoint < (NS_DRAM0_BASE + NS_DRAM0_SIZE)))
the above line (NS_DRAM0_BASE + NS_DRAM0_SIZE) = 0x100000000, which will
overflow 32bit and cause ERROR
SO add ULL to fix it

tested on compiler:
gcc version 10.2.1 20201103 (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16))
Signed-off-by: default avatarDarren Liang <lwp513@qq.com>
Change-Id: I1d769b0803142d37bd2968d765ab04a9c7c5c21a
325716c9
Name Last commit Last update
.husky build(hooks): add commitlint hook
bl1 Add PIE support for AARCH32
bl2 feat(fwu): initialize FWU driver in BL2
bl2u Avoid the use of linker *_SIZE__ macros
bl31 SMCCC/PCI: Handle std svc boilerplate
bl32 Add PIE support for AARCH32
common refactor(hw_crc32): renamed hw_crc32 to tf_crc32
docs refactor(tegra132): deprecate platform
drivers Merge changes Id93c4573,Ib7fea862,I44b9e5a9,I9e0ef734,I94d550ce, ... into integration
fdts feat(plat/arm): Introduce TC1 platform
include refactor(plat/ea_handler): Use default ea handler implementation for panic
lib errata: workaround for Neoverse V1 errata 2139242
licenses docs(license): rectify `arm-gic.h` license
make_helpers feat(fwu): initialize FWU driver in BL2
plat fix(plat/qemu): (NS_DRAM0_BASE + NS_DRAM0_SIZE) ADDR overflow 32bit
services services: Fix pmr_el1 rewrote issue in sdei_disaptch_event()
tools fix(tools/stm32image): improve the tool
.checkpatch.conf Re-apply GIT_COMMIT_ID check for checkpatch
.cz.json build(hooks): add Commitizen hook
.editorconfig .editorconfig: set max line length to 100
.gitignore build(hooks): add Husky configuration
.gitreview Specify integration as the default branch for git-review
Makefile feat(fwu): initialize FWU driver in BL2
commitlint.config.js revert(commitlint): disable `signed-off-by` rule
dco.txt Drop requirement for CLA in contribution.md
license.rst
package-lock.json
package.json
readme.rst
readme.rst

Trusted Firmware-A

Trusted Firmware-A (TF-A) is a reference implementation of secure world software for Arm A-Profile architectures (Armv8-A and Armv7-A), including an Exception Level 3 (EL3) Secure Monitor. It provides a suitable starting point for productization of secure world boot and runtime firmware, in either the AArch32 or AArch64 execution states.

TF-A implements Arm interface standards, including:

The code is designed to be portable and reusable across hardware platforms and software models that are based on the Armv8-A and Armv7-A architectures.

In collaboration with interested parties, we will continue to enhance TF-A with reference implementations of Arm standards to benefit developers working with Armv7-A and Armv8-A TrustZone technology.

Users are encouraged to do their own security validation, including penetration testing, on any secure world code derived from TF-A.

More Info and Documentation

To find out more about Trusted Firmware-A, please view the full documentation that is available through trustedfirmware.org.

Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.