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Varun Wadekar
authored
This patch enables the watchdog timer's interrupt as an FIQ
interrupt to the CPU. The interrupt generated by the watchdog
is connected to the flow controller for power management reasons,
and needs to be routed to the GICD for it to reach the CPU.
Change-Id: I9437b516da2c5d763eca72694ed7f3c7389b3d9e
Signed-off-by: 
Varun Wadekar <vwadekar@nvidia.com>| Name | Last commit | Last update |
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