Add workaround for errata 1073348 for Cortex-A76
Louis Mayencourt authored
Concurrent instruction TLB miss and mispredicted return instruction
might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to
prevent this.

Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58
Signed-off-by: default avatarLouis Mayencourt <louis.mayencourt@arm.com>
5c6aa01a