Louis Mayencourt
authored
Implicit Error Synchronization Barrier (IESB) might not be correctly
generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all
expection levels.
Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad
Signed-off-by: 
Louis Mayencourt <louis.mayencourt@arm.com>| Name | Last commit | Last update |
|---|---|---|
| .. | ||
| arch.h | ||
| arch_features.h | ||
| arch_helpers.h | ||
| asm_macros.S | ||
| assert_macros.S | ||
| console_macros.S | ||
| el3_common_macros.S | ||
| smccc_helpers.h | ||