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GICv3: Allow either G1S or G0 interrupts to be configured
Yatharth Kochar authored 
Currently the GICv3 driver mandates that platform populate
both G1S and G0 interrupts. However, it is possible that a
given platform is not interested in both the groups and
just needs to specify either one of them.

This patch modifies the `gicv3_rdistif_init()` & `gicv3_distif_init()`
functions to allow either G1S or G0 interrupts to be configured.

Fixes ARM-software/tf-issues#400

Change-Id: I43572b0e08ae30bed5af9334f25d35bf439b0d2b
6083c841
Name Last commit Last update
bl1 Merge pull request #689 from yatharth-arm/yk/plat_report_expn
bl2 Move spinlock library code to AArch64 folder
bl2u Introduce SEPARATE_CODE_AND_RODATA build flag
bl31 Introduce PSCI Library Interface
bl32 AArch32: add a minimal secure payload (SP_MIN)
common AArch32: resolve build error when LOG_LEVEL=50
docs Merge pull request #678 from soby-mathew/sm/PSCI_AArch32
drivers GICv3: Allow either G1S or G0 interrupts to be configured
fdts Remove support for legacy VE memory map in FVP
include Merge pull request #690 from soby-mathew/sm/level_sel_xlat
lib AArch32: Fix SCTLR context initialization
make_helpers Replace fip_create with fiptool
plat rockchip: fix the scu idle for rk3399
services Introduce PSCI Library Interface
tools fiptool: Fix typo in create and update usage functions
.checkpatch.conf Move checkpatch options in a configuration file
.gitignore Replace fip_create with fiptool
Makefile Move pmf headers to include/lib/pmf
acknowledgements.md Add Xilinx to acknowledgements file
contributing.md Update `contributing.md` CLA instructions
license.md Update year in copyright text to 2014
readme.md Update `readme.md` for v1.2 release