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n1sdp: setup multichip gic routing table
Manish Pandey authored 
N1SDP supports multichip configuration wherein n1sdp boards are
connected over high speed coherent CCIX link, for now only dual-chip
is supported.

Whether or not multiple chips are present is dynamically probed by
SCP firmware and passed on to TF-A, routing table will be set up
only if multiple chips are present.

Initialize GIC-600 multichip operation by overriding the default GICR
frames with array of GICR frames and setting the chip 0 as routing
table owner.

Change-Id: Ida35672be4bbf4c517469a5b330548d75e593ff2
Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
6799a370
Name Last commit Last update
bl1 TF-A: Add support for ARMv8.3-PAuth in BL1 SMC calls and BL2U
bl2 Refactor ARMv8.3 Pointer Authentication support code
bl2u TF-A: Add support for ARMv8.3-PAuth in BL1 SMC calls and BL2U
bl31 Neoverse N1 Errata Workaround 1542419
bl32 AArch32: Disable Secure Cycle Counter
common FDT helper functions: Respect architecture in PSCI function IDs
docs doc: Fix syntax erros in I/O storage layer plantuml diagrams
drivers gic/gic600: add support for multichip configuration
fdts fdts: stm32mp1: move FDCAN to PLL4_R
include gic/gic600: add support for multichip configuration
lib xlat_table_v2: Fix enable WARMBOOT_ENABLE_DCACHE_EARLY config
make_helpers Fix the CAS spinlock implementation
plat n1sdp: setup multichip gic routing table
services Merge changes from topic "jc/coverity-fixes" into integration
tools Remove RSA PKCS#1 v1.5 support from cert_tool
.checkpatch.conf Re-apply GIT_COMMIT_ID check for checkpatch
.editorconfig doc: Final, pre-release fixes and updates
.gitignore meson: Rename platform directory to amlogic
Makefile Update TF-A version to 2.2
dco.txt Drop requirement for CLA in contribution.md
license.rst doc: De-duplicate readme and license files
readme.rst doc: Formatting fixes for readme.rst
readme.rst

Trusted Firmware-A

Trusted Firmware-A (TF-A) is a reference implementation of secure world software for Arm A-Profile architectures (Armv8-A and Armv7-A), including an Exception Level 3 (EL3) Secure Monitor. It provides a suitable starting point for productization of secure world boot and runtime firmware, in either the AArch32 or AArch64 execution states.

TF-A implements Arm interface standards, including:

The code is designed to be portable and reusable across hardware platforms and software models that are based on the Armv8-A and Armv7-A architectures.

In collaboration with interested parties, we will continue to enhance TF-A with reference implementations of Arm standards to benefit developers working with Armv7-A and Armv8-A TrustZone technology.

Users are encouraged to do their own security validation, including penetration testing, on any secure world code derived from TF-A.

More Info and Documentation

To find out more about Trusted Firmware-A, please view the full documentation that is available through trustedfirmware.org.

Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.