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Xing Zheng
authored
Maybe the coreboot will reference the BL31 parameters (e.g the TZRAM_BASE
and TZRAM_SIZE for DDR secure regions), we can split them and don't have
to hardcode the range in two places.
Signed-off-by: 
Xing Zheng <zhengxing@rock-chips.com>| Name | Last commit | Last update |
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