refactor(plat/st): map DDR secure at boot
Yann Gautier authored
In BL2, the DDR can be mapped as secured in MMU, as no other SW
has access to it during its execution.
The TZC400 configuration is also updated to reflect this. When using
OP-TEE, the TZC400 is reconfigured at the end of BL2, to match OP-TEE
mapping. Else, SP_min will be in charge to reconfigure TZC400 to set
DDR non-secure.

Change-Id: Ic5ec614b218f733796feeab1cdc425d28cc7c103
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
c1ad41fb
Name Last commit Last update
..
allwinner allwinner: H616: Add reserved-memory node to DT
amlogic Plat AXG: Fix PLAT_MAX_PWR_LVL value
arm Merge changes from topic "sb/measured-boot" into integration
brcm Merge "driver: brcm: add USB driver" into integration
common Fix typos and misspellings
hisilicon plat/hisilicon: do not keep mmc_device_info in stack
imx Merge changes from topic "imx8m-sdei" into integration
intel/soc plat/intel: do not keep mmc_device_info in stack
layerscape Don't return error information from console_flush
marvell fix(plat/marvell/a3720/uart): fix UART parent clock rate determination
mediatek feat(plat/mediatek/mt8195): add SPM suspend driver
nvidia/tegra refactor(plat/nvidia): use SOC_ID defines
nxp feat(plat/nxp/lx2): add SUPPORTED_BOOT_MODE definition
qemu refactor(plat/qemu): increase the non-secure DRAM size
qti qti: spmi_arb: Fix NUM_APID and REG_APID_MAP() argument
renesas renesas: rzg: Add support to identify EK874 RZ/G2E board
rockchip plat/rockchip: Use common gicv2.mk
rpi rpi4: update the iobase constant
socionext Don't return error information from console_flush
st refactor(plat/st): map DDR secure at boot
ti/k3 plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0
xilinx fix(plat/xilinx/versal): use sync method for blocking calls