Xing Zheng
authored
Maybe the coreboot will reference the BL31 parameters (e.g the TZRAM_BASE
and TZRAM_SIZE for DDR secure regions), we can split them and don't have
to hardcode the range in two places.
Signed-off-by: 
Xing Zheng <zhengxing@rock-chips.com>| Name | Last commit | Last update |
|---|---|---|
| .. | ||
| shared | ||
| addressmap.h | ||
| plat.ld.S | ||
| plat_sip_calls.h | ||
| platform_def.h | ||